Patents by Inventor Mark Levence Leadbeater
Mark Levence Leadbeater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9159929Abstract: A monomer for use in manufacturing a conjugated polymer, the monomer having a structure as shown formula (2): Ar1, Ar2 and Ar3 are independently selected from optionally substituted aryl or heteroaryl, X1 and X3 both independently comprise a leaving group capable of participating in polymerization and Z represents a direct bond or an optionally substituted bridging atom.Type: GrantFiled: March 18, 2013Date of Patent: October 13, 2015Assignees: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED, CDT OXFORD LIMITEDInventors: Mark Levence Leadbeater, Sophie Heidenhain, Annette Steudel, Daniel Hicks
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Patent number: 7989255Abstract: A method of forming an optical device comprising the steps of: providing a substrate comprising a first electrode capable of injecting or accepting charge carriers of a first type; forming over the first electrode a first layer that is at least partially insoluble in a solvent by depositing a first semiconducting material that is free of cross-linkable vinyl or ethynyl groups and is, at the time of deposition, soluble in the solvent; forming a second layer in contact with the first layer and comprising a second semiconducting material by depositing a second semiconducting material from a solution in the solvent; and forming over the second layer a second electrode capable of injecting or accepting charge carriers of a second type wherein the first layer is rendered at least partially insoluble by one or more of heat, vacuum and ambient drying treatment following deposition of the first semiconducting material.Type: GrantFiled: May 12, 2009Date of Patent: August 2, 2011Assignees: Cambridge Display Technology Limited, General Electric CompanyInventors: Craig Edward Murphy, Salvatore Cina, Timothy Butler, Matthew Roberts, Nalinkumar Lallubhai Patel, Clare Louise Foden, Mark Levence Leadbeater, Daniel Alan Forsythe, Robert Sidney Archer, Nicholas de Brissac Baynes, Nathan Luke Phillips, Anil Raj Duggal, Jie Liu
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Publication number: 20090227052Abstract: A method of forming an optical device comprising the steps of: providing a substrate comprising a first electrode capable of injecting or accepting charge carriers of a first type; forming over the first electrode a first layer that is at least partially insoluble in a solvent by depositing a first semiconducting material that is free of cross-linkable vinyl or ethynyl groups and is, at the time of deposition, soluble in the solvent; forming a second layer in contact with the first layer and comprising a second semiconducting material by depositing a second semiconducting material from a solution in the solvent; and forming over the second layer a second electrode capable of injecting or accepting charge carriers of a second type wherein the first layer is rendered at least partially insoluble by one or more of heat, vacuum and ambient drying treatment following deposition of the first semiconducting material.Type: ApplicationFiled: May 12, 2009Publication date: September 10, 2009Applicants: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED, GENERAL ELECTRIC COMPANYInventors: Craig Edward Murphy, Salvatore Cina, Timothy Butler, Matthew Roberts, Nalinkumar Lallubhai Patel, Clare Louise Foden, Mark Levence Leadbeater, Daniel Alan Forsythe, Robert Sidney Archer, Nicholas de Brissac Baynes, Nathan Luke Phillips, Anil Raj Duggal, Jie Liu
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Patent number: 7531377Abstract: A method of forming an optical device comprising the steps of: providing a substrate comprising a first electrode capable of injecting or accepting charge carriers of a first type; forming over the first electrode a first layer that is at least partially insoluble in a solvent by depositing a first semiconducting material that is free of cross-linkable vinyl or ethynyl groups and is, at the time of deposition, soluble in the solvent; forming a second layer in contact with the first layer and comprising a second semiconducting material by depositing a second semiconducting material from a solution in the solvent; and forming over the second layer a second electrode capable of injecting or accepting charge carriers of a second type wherein the first layer is rendered at least partially insoluble by one or more of heat, vacuum and ambient drying treatment following deposition of the first semiconducting material.Type: GrantFiled: September 3, 2003Date of Patent: May 12, 2009Assignee: Cambridge Display Technology LimitedInventors: Craig Edward Murphy, Salvatore Cina, Timothy Butler, Matthew Roberts, Nalinkumar Lallubhai Patel, Clare Louise Foden, Mark Levence Leadbeater, Daniel Alan Forsythe, Robert Sidney Archer, Nicholas de Brissac Baynes, Nathan Luke Phillips, Anil Raj Duggal, Jie Liu
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Patent number: 6657222Abstract: A photon source, comprising a first semiconductor region having excess carriers with a first conductivity type, and a second semiconductor region having excess carriers with a second conductivity type, the first and second conductivity types being opposing conductivity types; means for creating a surface acoustic wave (SAW) travelling from the first semiconductor region to the second semiconductor region such that excess carriers from the first semiconductor region are carried by the wave to the second region and quantizing means for quantizing the carrier transport caused by the wave, such that the number of carriers introduced into the second semiconductor region can be controlled to the accuracy of a single carrier.Type: GrantFiled: September 14, 2000Date of Patent: December 2, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Clare Louise Foden, Mark Levence Leadbeater, Valery Talyansky
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Patent number: 6031245Abstract: A semiconductor device is presented which exhibits both interband and intraband tunnelling. The device comprises two active layers (21, 23) which are sandwiched between two barrier layers (3, 5). These layers are located between first and second terminals (7, 9). The active layers (21, 23) are chosen such that the conduction band edge (27) of the first active layer (21) having a lower energy than the valence band edge (25) of the second active layer (23);the first active layer (21) having a first confined conduction band energy level (29) with an energy higher than that of the conduction band edge (27) of the first active layer (21);the second active layer (23) having a first confined valence band energy level (33) with an energy lower than that of the valence band edge (25) of the second active layer (23);wherein the first confined valence band energy level (33) and the first confined conduction band energy level (29) are located such that the device can exhibit both intraband and interband tunnelling.Type: GrantFiled: December 11, 1998Date of Patent: February 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Nalin Kumar Patel, Mark Levence Leadbeater, Llewellyn John Cooper