Patents by Inventor Mark Leverington

Mark Leverington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230409530
    Abstract: In some examples, a computing device stores root metadata data structures (DSs) together in a group root metadata filesystem block, and stores, in a data filesystem block, at least first file data referenced by the first root metadata DS and second file data referenced by a second root metadata DS. The computing device may determine a reference count of the data filesystem block based on the first file data referenced by the first root metadata DS and the second file data referenced by the second root metadata DS. In addition, the computing device may determine a third file data having content that matches the first file data and referenced by a third root metadata DS. The computing device may update the third root metadata DS to reference the first file data, and update the reference count of the data filesystem block based on updating the third root metadata DS.
    Type: Application
    Filed: January 12, 2021
    Publication date: December 21, 2023
    Inventors: Jonathan SMITH, Mark LEVERINGTON, Simon CROSLAND
  • Publication number: 20090046820
    Abstract: Serial data transmission is performed using a serial data signal (8) with an associated clock signal (10) having sampling-trigger characteristics within the clock signal for controlling when the serial data signal is sampled by the receiver (2). Instead of reducing the clock signal frequency to a level where minimum setup time and minimum hold time requirements are met for every serial bit irrespective of its value, the technique instead runs at a higher frequency assuming that the bit value will not change and when a change in bit value does occur extends the time between sampling-trigger characteristics and extends assertion of either the preceding bit in the case of hold time requirements or the following bit in the case of setup time requirements. The technique is particularly useful in serial communication of diagnostic data with integrated circuits (2).
    Type: Application
    Filed: February 15, 2006
    Publication date: February 19, 2009
    Inventors: Mark Clark, Mark Leverington
  • Patent number: 5493585
    Abstract: An adaptive equalizer includes a digital linear filter having adjustable weighting factors and which is connected to a summator and a control unit so as to form two filter loops, one direct and the other recursive, the filter being shared in both loops. The control unit provides a weighting factor which establishes a selected relative proportioning of the data signals which traverse each loop, so that the equalizer is proportioned as to the degree to which it provides direct filtering and the degree to which it provides recursive filtering. Recursive filtering is employed to the maximum extent consistent with operating stability, the relative proportion of direct filtering being increased as necessary in order to maintain stability during equalization of any particular received data signal.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: February 20, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Mark Leverington, Pascal Hayet, Eric Finco