Patents by Inventor Mark Levy

Mark Levy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11925586
    Abstract: A surgical platform and trolley assembly and an interface of a robotic system are provided. The surgical platform and trolley assembly includes a trolley portion and a surgical platform portion. The trolley portion supports the surgical platform portion, and affords positioning and repositioning of the surgical platform portion relative to the interface of the robotic system. An end portion of the surgical platform portion is attachable relative to the robotic system via engagement to the interface.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: March 12, 2024
    Assignee: MAZOR ROBOTICS LTD.
    Inventors: Roy K. Lim, Arik A. Levy, Katharine E. Darling, Mark C. Dace, Yonatan Ushpizin
  • Publication number: 20240009668
    Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a semiconductor substrate including a trench and a layer stack on the semiconductor substrate. The layer stack includes a first layer, a second layer between the first layer and the semiconductor substrate, and an opening penetrating through the first layer and the second layer to the trench. The structure further comprises a third layer inside the opening in the layer stack. The third layer, which comprises a semiconductor material, obstructs the opening to define a cavity inside the trench.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Ramsey Hazbun, Siva P. Adusumilli, Mark Levy, Bartlomiej Jan Pawlak
  • Publication number: 20240014101
    Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Ramsey Hazbun, Cameron Luce, Siva P. Adusumilli, Mark Levy
  • Patent number: 11768337
    Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 26, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Spencer Porter, Mark Levy, Siva P. Adusumilli, Yusheng Bian
  • Publication number: 20230223254
    Abstract: Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Inventors: Ramsey Hazbun, Mark Levy, Alvin Joseph, Siva P. Adusumilli
  • Publication number: 20230125886
    Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Inventors: Steven M. Shank, Anthony K. Stamper, Venkata N.R. Vanukuru, Mark Levy
  • Publication number: 20230121393
    Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: Siva P. Adusumilli, Mark Levy, Jeonghyun Hwang
  • Patent number: 11567277
    Abstract: Structures that include a distributed Bragg reflector and methods of fabricating a structure that includes a distributed Bragg reflector. The structure includes a substrate, an optical component, and a distributed Bragg reflector positioned between the optical component and the substrate. The distributed Bragg reflector includes airgaps and silicon layers that alternate in a vertical direction with the airgaps to define a plurality of periods.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Yusheng Bian, Mark Levy, Siva P. Adusumilli
  • Patent number: 11569374
    Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Siva P. Adusumilli, Mark Levy, Jeonghyun Hwang
  • Publication number: 20230008201
    Abstract: A content management system and/or client device can enable a user to initiate a quick play mode where a content category and content medium are selected for the user. A client device and/or a content management system can select a content medium for a user based on one or more factors, such as the content category. Certain content categories of content can be preferably delivered in certain content mediums. In some embodiments, a content management system and/or client device can select a content medium for a user based on contextual data gathered from the user. Contextual data can be data describing the user's current state and/or environment. For example, contextual data can include data such as the time of day, geographic location, etc.
    Type: Application
    Filed: February 28, 2022
    Publication date: January 12, 2023
    Inventors: Thomas Alsina, Arvind S. Shenoy, Daniel Cartoon, Jeffrey L. Robbin, Mark Levy
  • Publication number: 20220413232
    Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Spencer Porter, Mark Levy, Siva P. Adusumilli, Yusheng Bian
  • Publication number: 20220392888
    Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Mark Levy, Jeonghyun Hwang, Siva P. Adusumilli
  • Patent number: 11469225
    Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark Levy, Jeonghyun Hwang, Siva P. Adusumilli
  • Patent number: 11437522
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: September 6, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Michel J. Abou-Khalil, Steven M. Shank, Mark Levy, Rajendran Krishnasamy, John J. Ellis-Monaghan, Anthony K. Stamper
  • Publication number: 20220190145
    Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
  • Patent number: 11362201
    Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: June 14, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
  • Publication number: 20220173233
    Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 2, 2022
    Inventors: Siva P. Adusumilli, Mark Levy, Jeonghyun Hwang
  • Publication number: 20220122963
    Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a <111> crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 21, 2022
    Inventors: Mark Levy, Jeonghyun Hwang, Siva P. Adusumilli
  • Patent number: 11264457
    Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Mark Levy, Siva P. Adusumilli, Steven M. Shank, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 11262972
    Abstract: A content management system and/or client device can enable a user to initiate a quick play mode where a content category and content medium are selected for the user. A client device and/or a content management system can select a content medium for a user based on one or more factors, such as the content category. Certain content categories of content can be preferably delivered in certain content mediums. In some embodiments, a content management system and/or client device can select a content medium for a user based on contextual data gathered from the user. Contextual data can be data describing the user's current state and/or environment. For example, contextual data can include data such as the time of day, geographic location, etc.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 1, 2022
    Assignee: Apple Inc.
    Inventors: Thomas Alsina, Arvind S. Shenoy, Daniel Cartoon, Jeffrey L. Robbin, Mark Levy