Abstract: Technology for reading memory cells in a cross-point architecture. A memory system reads one memory cell in each module in parallel. The memory system performs two reads of the memory cells with a first read using a first reference signal and a second read using a second reference signal instead of the first reference signal. The second reference signal has a different magnitude from the first reference signal in order to compensate for differences between the modules.

Abstract: Technology for programming selector-only memory cells in a cross-point memory structure. The threshold switching memory element may include, but is not limited to, an Ovonic Threshold Switch (OTS). The memory system removes Vth drift in the threshold switching memory elements prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having the two polarities are applied to program the cells to two states.

Abstract: Technology for lowering the threshold voltage of a threshold switching selector in a programmable resistance memory cell. The memory system applies a first control signal to circuitry to establish a first resistance of transistors in series with the programmable resistance memory cell, a word line and a bit line when controlling the circuitry to apply a voltage across the programmable resistance memory cell to lower a threshold voltage of a threshold switching selector in the programmable resistance memory cell. The memory system applies a second control signal to the circuitry to establish a second resistance of the circuitry in series with the programmable resistance memory cell, the word line and the bit line to read the selected programmable resistance memory. The second resistance is lower than the first resistance.

Abstract: An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.

Abstract: An apparatus includes memory array having a first memory cell including a first two-terminal element having first and second threshold voltages, a second memory cell including a second two-terminal element having third and fourth threshold voltages, and a control circuit coupled to the memory array. The control circuit is configured to cause the first two-terminal element to have the first threshold voltage, and cause the second two-terminal element to have either the third threshold voltage or the fourth threshold voltage, apply a third voltage signal that increases at a first ramp rate to the first memory cell and the second memory cell, determine that the first memory cell switches from a non-conducting state to a conducting state, and read the second memory cell using the third voltage signal a first predetermined delay time after the first memory cell switches from the non-conducting state to the conducting state.

Abstract: Technology is disclosed for programming selector-only memory cells in a cross-point memory structure. The threshold switching memory element may include, but is not limited to, an Ovonic Threshold Switch (OTS). The memory system removes the effects of Vth drift in the reading of threshold switching memory elements. Each bit of data is written to a pair of selector-only memory cells with opposite polarities so that, when read with the same polarity, one has a high ON threshold and the other has a low ON threshold, but the bits are differentiated by which of the pair of selector-only memory cells has which ON threshold differs. Although the turn on voltage of both the high ON threshold state and the low ON threshold state drifts, they largely drift at the same rate so that a differential read of the memory cell pair can be used over an extended read period.

Abstract: An apparatus includes a first memory cell coupled between a first word line and a first bit line and series coupled with a first word line resistance and first bit line resistance, and a second memory cell coupled between a second word line and a second bit line and series coupled with a second word line resistance and second bit line resistance. The first memory cell includes a first hard mask including a first hard mask material having a first resistivity, and the second memory cell includes a second hard mask including a second hard mask material having a second resistivity lower than the first resistivity. The first hard mask is configured to compensate for a difference between a first sum of the first word line resistance and the first bit line resistance and a second sum of the second word line resistance and the second bit line resistance.

Abstract: Technology is disclosed for seasoning (forming) threshold switching selectors in a cross-bar array. The Vth of the threshold switching selectors in a cross-bar array is progressively lowered over a number of seasoning cycles. The memory cell that is selected for seasoning of its threshold switching selector has a seasoning signal apply to the cell. The magnitude of the seasoning signal is progressively lowered each seasoning cycle. The progressive lowering of the Vth of the threshold switching selectors “partially forms” the threshold switching selectors each cycle as the Vth of the threshold switching selectors is only fully formed after a number of seasoning cycles.

Abstract: Technology for programming selector-only memory cells in a cross-point memory structure. The threshold switching memory element may include, but is not limited to, an Ovonic Threshold Switch (OTS). The memory system removes Vth drift in the threshold switching memory elements prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having the two polarities are applied to program the cells to two states.

Abstract: Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.

Abstract: Technology for reading programmable resistance memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. Each memory cell has a capacitor associated therewith. One of the electrodes of the capacitor may be formed from a conductive region of the cell in contact with the threshold switching selector. When the threshold switching selector turns on the voltage across the memory cell may rapidly drop, thereby resulting in a snapback current. The capacitor is able to absorb at least some of the snapback current to therefore reduce or even eliminate snapback current flow through the memory element.

Abstract: An apparatus is provided that includes a memory cell having a reversible resistance-switching memory element coupled in series with a selector element. The selector element has a first resistance. The resistance-switching memory element is configured to reversibly switch between a second resistance and a third resistance. The memory cell may be selectively configured as either a re-writeable memory cell or a one-time programmable memory cell. The memory cell functions as a one-time programmable memory cell regardless of whether the resistance-switching memory element has the second resistance, the third resistance, or is electrically shorted.

Abstract: Technology for reading memory cells in a cross-point architecture. A memory system reads one memory cell in each module in parallel. The memory system performs two reads of the memory cells with a first read using a first reference signal and a second read using a second reference signal instead of the first reference signal. The second reference signal has a different magnitude from the first reference signal in order to compensate for differences between the modules.

Abstract: User engagement is detected and used to control operation of a computing device. User engagement is detected by a sensor such as a camera that identifies if a user's face is oriented towards a display device. If the user is not facing the display device, the sensor determines that the user is unengaged. The computing device is thus able to perform a power-saving operation, such as dimming the display device, when the user is unengaged. The computing device includes an API that abstracts sensor data into a user engagement signal indicating that the user is either engaged or unengaged. The OS and applications running on the computing device act on the user engagement signal provided by the API without communicating directly with the sensor. The user engagement signal may be provided as an input to a state machine.

Abstract: An apparatus is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistance-switching memory element coupled in series with a selector element that has a threshold voltage. The control circuit is configured to use a first pulse having a first polarity to first access the memory cell, and use a second pulse having the first polarity to second access the memory cell and read the memory cell. The first pulse is configured to reduce a rate of threshold voltage drift of the selector element.

Abstract: An apparatus is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistance-switching memory element coupled in series with a selector element that has a threshold voltage. The control circuit is configured to use a first pulse having a first polarity to first access the memory cell, use a second pulse having a second polarity opposite the first polarity to second access the memory cell, and use a third pulse having the first polarity to third access the memory cell. The third pulse is configured to reduce a rate of threshold voltage drift of the selector element.