Abstract: A system that comprises a plurality of reconfigurable processors. Virtual machines are configurable across multiple reconfigurable processors in the plurality of reconfigurable processors. A first virtual machine in the virtual machines is configured in a set of configurable units that is confined to a first reconfigurable processor in the plurality of reconfigurable processors. A second virtual machine in the virtual machines is configured in a set of configurable units that spans both the first reconfigurable processor and a second reconfigurable processor in the plurality of reconfigurable processors.

Abstract: A reconfigurable data processor comprises an array of configurable units including a plurality of tiles and a bus system. The bus system includes boundary switches on tile boundaries, configurable to partition the array into sets of configurable units spanning one or more tiles. A configuration controller is configured to load a configuration file to form a virtual machine across multiple tiles by setting the boundary switches to isolate the virtual machine.

Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system. The array includes a plurality of atomic partitionable groups, each comprising a minimum set of configurable units usable to compose a virtual machine. The bus system is connected to the array and configurable to isolate the atomic partitionable groups. A configuration controller is configured to allocate one or more atomic partitionable groups to a virtual machine for executing an application graph. Configurable units of each group allocated to a virtual machine are isolated from communicating with configurable units in groups allocated to other virtual machines via the bus system.

Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system includes a grid of switches connected to the array of configurable units. Each switch has a plurality of ports and a switch port disable register configurable to selectively disable one or more of the plurality of ports. A configuration controller is configured to load a configuration file that sets the switch port disable registers to partition the array into a plurality of isolated sets of configurable units. Each set is blocked from communicating with configurable units outside the set via the bus system.

Abstract: A tile of an embodiment of a coarse-grain reconfigurable architecture (CGRA) is based on an array of fused compute-memory units (FCMUs), pattern memory units (PMUs), and/or pattern compute units (PCUs) arranged in two dimensions, M×N. Unless clearly noted from context, any reference to a FCMU, PCU, or PMU may refer to one or more of the other units. The communication between a set of FCMUs is performed over a (M+1)×(N+1) switch fabric called the array-level network (ALN) where each switch has connections to its neighboring FCMUs and to neighboring switches in each of the four directions.

Abstract: System and method for port arbitration in a switch network for dataflow computing systems, particularly in computer systems having a plurality reconfigurable processing units interconnected using switches. A switch network comprises a switch, a plurality of nodes coupled to the switch, and a Dynamic Equality of Service (DEoS) arbiter. The DEoS arbiter may perform operations to arbitrate among input ports of the switch to make a through-connection. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. DEoS metrics may include DES counters, and/or quantization ranges of DEoS counters, associated with the source nodes.

Abstract: A method comprises a Dynamic Equality of Service (DEoS) arbiter of a switch computing port DEoS metrics based on dynamic input activity of source nodes into input ports of the switch. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. The port DEoS metrics can be based on node DEoS metrics including DEoS counters, and/or quantization ranges of DEoS counters, associated with the source nodes. A switching apparatus comprises a switch, a plurality of nodes coupled to the switch, and a DEoS arbiter. The switching apparatus can further comprise a first and second DEoS counter. The DEoS arbiter can perform operations of the method to arbitrate among input ports of the switch to make a through-connection.

Abstract: A method and system for unloading configuration data in a reconfigurable processor array comprises a bus system, and array of processor units connected to bus system, the processor units in the array including configuration data stores to store unit files comprising plurality of subfiles of configuration data particular to corresponding processor units. A configuration unload controller is connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to plurality of the processor units in array to unload the unit files particular to corresponding processor units, the unit files each comprising plurality of ordered sub-files, receiving sub-files via bus system from the array of process units, and assembling an unload configuration file by arranging the received subfiles in memory according to the process unit of the unit file of which the subfile is a part, and order of the subfile in unit file.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system is connected to the array of configurable units. The bus system includes a top level network and an array level network. The top level network is connected to an external data interface for communication with memory outside of the array of configurable units. The array level network is connected to configurable units in the array of configurable units.

Abstract: A method comprises a Dynamic Equality of Service (DEoS) arbiter of a switch computing port DEoS metrics based on dynamic input activity of source nodes into input ports of the switch. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. The port DEoS metrics can be based on node DEoS metrics including DEoS counters, and/or quantization ranges of DEoS counters, associated with the source nodes. A switching apparatus comprises a switch, a plurality of nodes coupled to the switch, and a DEoS arbiter. The switching apparatus can further comprise a first and second DEoS counter. The DEoS arbiter can perform operations of the method to arbitrate among input ports of the switch to make a through-connection.

Abstract: A reconfigurable data processor includes a plurality of configurable units, and a configuration controller. The configuration controller is configured to start execution of a first application graph in a first set of configurable units. Then, concurrently with the execution of the first application graph in the first set of configurable units, the configuration controllers receive a command to load a configuration file into a second set of configurable units and obtain the configuration file. The configuration file contains information to configure the second set of configurable units to execute a second application graph. The configuration file is then loaded into the second set of configurable units and execution of the second application graph is started in the second set of configurable units.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

Abstract: A reconfigurable data processor includes a plurality of configurable units, and a configuration controller. The configuration controller is configured to start execution of a first application graph in a first set of configurable units. Then, concurrently with the execution of the first application graph in the first set of configurable units, the configuration controllers receive a command to load a configuration file into a second set of configurable units and obtain the configuration file. The configuration file contains information to configure the second set of configurable units to execute a second application graph. The configuration file is then loaded into the second set of configurable units and execution of the second application graph is started in the second set of configurable units.

Abstract: A functional unit for a data processor comprises an input register to store a variable X; a first circuit, having an input connected to the input register and an output, to generate a value eX on its output; a second circuit, having an input connected to the input register and an output, to generate an output which is a value (tan h(X/2)+1)/2 on its output; a comparator, having an input connected to the input register and an output, to generate a line on its output based on a comparison between X and a constant; and a selector to select between inputs connected to the outputs of the first circuit and the second circuit, in response to the output of the comparator, and provide an output representing a value sigmoid(X).

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.

Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.