Abstract: The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.

Abstract: A master-slave-master latch circuit for loading data vertically or horizontally. A first master latch is coupled to an input terminal for receiving data. Under control of a clock, the data is transferred from the master latch to a slave latch input terminal. Under control of the slave latch clock, the data is shifted horizontally into the slave latch. Under control of a further horizontal shift clock the data is shifted to a further master latch. The slave circuits are organized in a vertical column fashion so that data may be shifted vertically up or down the slave latches as provided from the master latch. Feedback circuits from the master latch to various positions within the slave latch column permit the data to be selectively transferred from one horizontal level to the prior horizontal level for placing in the vertical column.

Abstract: A memory circuit has a plurality of data storage locations and an address associated with each data storage location. A first decoded address storage circuit stores a first decoded memory address and outputs the stored first decoded memory address. A second decoded address storage circuit stores a second decoded memory address and outputs the stored second decoded memory address. An address access circuit is coupled to the output of the first decoded address storage circuit and accesses the data storage location associated with the first decoded memory address in response to the first decoded memory address being output from the first decoded address storage circuit. A control circuit is coupled to the first decoded address storage circuit for controlling the transfer of decoded memory address information from the second decoded address storage circuit to the first decoded address storage circuit.

Abstract: According to the present invention, a structure and method provides for single bit failures of an integrated circuit memory device to be analyzed. According to the method for analyzing a single bit failure of an integrated circuit memory device, a test mode is entered, bitline load devices of the integrated circuit memory device are turned off, a single bit of the integrated circuit memory device is selected, the device is placed into a write mode, a plurality of bitlines true and a plurality of bitlines complement of the integrated circuit memory device not associated with the single bit are then set to a low logic level, the bitline true and the bitline complement associated with the single bit is connected to a supply bus and a supply complement bus which is connected to test pads. Finally, the electrical characteristics of the single bit can be monitored on the test pads.

Abstract: According to the present invention, column redundancy circuitry provides column redundancy to an integrated circuit memory device having a multiple block memory architecture with limited programming overhead and maximum flexibility. Column redundancy circuitry is placed within a block of the multiple block memory architecture and may be placed within multiple blocks of the integrated circuit device as required. The column redundancy circuitry has a column select multiplexing circuit, an input/output select circuit for a redundant column of the memory array, and a redundant column select circuit to drive the input/output select circuit for a redundant column. Fuse circuitry contained within column select multiplexing circuit disables a bad prime column by removing fuses in order to isolate the bitline pair associated with the bad column from the read and write busses of the memory array.

Abstract: An apparatus generates a bus-driver enable signal that enables a bus driver to couple a data signal from a sense amplifier to a data bus. A first circuit generates an equilibration pulse to equilibrate the sense amplifier, and a bus-driver enable circuit generates the bus-driver enable signal. A bus-driver disable circuit generates in response to the equilibration pulse a bus-driver disable signal for disabling the enable circuit at least until the data signal becomes valid.

Abstract: An apparatus generates a bus-driver enable signal that enables a bus driver to couple a data signal from a sense amplifier to a data bus. A first circuit generates an equilibration pulse to equilibrate the sense amplifier, and a bus-driver enable circuit generates the bus-driver enable signal. A bus-driver disable circuit generates in response to the equilibration pulse a bus-driver disable signal for disabling the enable circuit at least until the data signal becomes valid.

Abstract: A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor.

Abstract: A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

Abstract: A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

Abstract: A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence.

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.