Patents by Inventor MARK M. LACEY

MARK M. LACEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DYNAMIC SUBROUTINE LINKAGE OPTIMIZING SHADER PERFORMANCE
    Publication number: 20170039754
    Abstract: Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
    Type: Application
    Filed: July 12, 2016
    Publication date: February 9, 2017
    Inventors: MICHAEL V. ONEPPO, CRAIG PEEPER, ANDREW L. BLISS, JOHN L. RAPP, MARK M. LACEY
  • SHADER INTERFACES
    Publication number: 20090322751
    Abstract: Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 31, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: MICHAEL V. ONEPPO, CRAIG PEEPER, ANDREW L. BLISS, JOHN L. RAPP, MARK M. LACEY