Patents by Inventor Mark M. Schaffer

Mark M. Schaffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus
    Patent number: 8599886
    Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 3, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Martyn R. Shirlen, Richard G. Hofmann, Mark M. Schaffer
  • Methods and Apparatus for Reducing Transfer Qualifier Signaling on a Two-Channel Bus
    Publication number: 20120051373
    Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 1, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Martyn R. Shirlen, Richard G. Hofmann, Mark M. Schaffer
  • Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations
    Patent number: 4926374
    Abstract: The invention concerns a residue checking apparatus which uses common circuitry to conduct residue checking of the outcome of an arithmetic operation which may be an add, a subtract, a multiply, a divide, or a square root operation.
    Type: Grant
    Filed: November 23, 1988
    Date of Patent: May 15, 1990
    Assignee: International Business Machines Corporation
    Inventor: Mark M. Schaffer