Abstract: A system performance control component, and method therefor, for configuring at least one system performance parameter within a signal processing system. The system performance control component is arranged to receive an indication of an address of a memory access performed by at least one signal processing component, compare the received indication of an address of a memory access to at least one address value, and configure at least one system performance parameter based at least partly on the comparison of the received indication of an address of a memory access to at least one address value.

Abstract: An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.

Abstract: An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element.

Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

Abstract: A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.

Abstract: An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element.

Abstract: A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialisation data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialisation data.

Abstract: A method for setting one or more breakpoints within executable program code of an embedded device is described. The method comprises copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which a breakpoint is to be set, into at least one area of overlay memory replacing within the overlay memory the at least one instruction at which a breakpoint is to be set with a breakpoint operation code, and enabling a mapping of the at least one area of NVM, comprising the at least one instruction at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within the embedded device.

Abstract: A logic analyzer embedded in a data processor includes a state processing unit for providing state machines for storing state conditions of functional blocks of the data processor and triggering sequences of states with corresponding actions based on True/False evaluation of state conditions. The configurations of the state machines that can be selected by the user include different combinations of a first clock frequency CLK1, which is the fastest distributed clock frequency of the device, and a second sub-multiple clock frequency CLK1/X for processing different sequences of states and synchronizing state conditions of the state machines. The state processing unit performs sample operations capturing assertion events synchronized by the first clock frequency CLK1, and hold operations on captured assertion events during periods defined by the first or second clock frequency CLK1 or CLK1/X as selected by the user.

Abstract: A system includes a processor configured to execute a first interrupt; an interrupt controller, coupled to the processor, and configured to store one or more pending interrupts; and a sequence processing unit, coupled to the processor and the interrupt controller, and configured to receive an identifier of the first interrupt, receive an identifier corresponding to each of the one or more pending interrupts, and provide trigger information to a state condition logic in response to one or more of the identifiers of the one or more pending interrupts and the identifier of the first interrupt, wherein the trigger information is used to determine a trace or debug action responsive to the trigger information.

Abstract: A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.

Abstract: A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.

Abstract: A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates.

Abstract: A fault tolerant electronic braking system for a vehicle has a brake pedal arranged to provide an electronic signal in response to operation thereof. A number of braking nodes are coupled to the brake pedal, each node being arranged to control a brake actuator. Each brake node has a controller arranged for processing the first signal to provide a second signal for controlling the brake actuator, and for providing third signals for transmission to the other control means. The third signals are the expected second signal results of the other controllers. Each controller is arranged to compare the second signal with the third signals received from the other controllers such that errors detected between the second and third signals indicate faults in the controllers.

Abstract: A microprocessor module is arranged to be coupled to a communications network having a number of distributed modules. Each module is arranged to transmit status signals relating to the status of other modules. The microprocessor module includes a microcontroller arranged to control functions of the module and a reset arrangement coupled to the network and arranged for providing a reset signal to reset the microcontroller in dependence upon a reset condition. The reset condition is determined by a voting scheme applied to the status signals received from the plurality of modules.