Abstract: An interface assembly comprises a nasal mask that includes a seal having a rolling portion. The rolling portion of the seal rolls over a portion of a clip that secures the seal to a frame. The frame has a ball and socket connection to a connector. The connector comprises an elbow having integrally formed exhaust holes and a swivel.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A balloon-manipulating device for a balloon catheter, methods of making, and methods of use. The balloon-manipulating device includes a tubular body, a longitudinal hole through a least a portion of the tubular body, one or more balloon-compressing pieces of a sidewall of the tubular body, and one or more balloon-letting through holes through the sidewall. The longitudinal hole may extend from an opened proximal end of the tubular body to at least a distal end portion of the tubular body, and is configured for inserting a balloon-catheter shaft therein. Each of the one or more balloon-compressing pieces is configured for compressing a different portion of an inflated balloon-catheter balloon when the balloon-manipulating device is disposed over the balloon. Each of the one or more balloon-letting through holes is configured for allowing therethrough a different portion of an inflated balloon-catheter balloon when the balloon-manipulating device is disposed over the balloon.

Abstract: The present disclosure pertains to a system for controlling a leak flow rate during respiratory therapy. The system is configured to determine a leak flow rate necessary for CO2 expulsion for an individual subject and facilitate control of the leak flow rate during therapy such that the system exhausts substantially the entire exhaled volume of gas during an expiration of the subject. The system facilitates control of the leak flow rate during therapy via an adjustable leak valve. Determining the leak flow rate for the subject and facilitating control of the leak rate may minimize noise from air flow in the system, minimize the power draw needed by a pressure generator of the system, reduce a loss of medicine added to the respiratory therapy gas, and/or have other advantages, while still expelling the desired amount of CO2.

Abstract: A balloon-manipulating device for a balloon catheter includes, in some embodiments, a tubular body, a longitudinal hole through a least a portion of the tubular body, one or more balloon-compressing pieces of a sidewall of the tubular body, and one or more balloon-letting through holes through the sidewall. The longitudinal hole extends from an opened proximal end of the tubular body to at least a distal end portion of the tubular body. The longitudinal hole is configured for inserting a balloon-catheter shaft in the longitudinal hole. Each balloon-compressing piece is configured for compressing a different portion of an inflated balloon-catheter balloon when the balloon-manipulating device is disposed over the balloon. Each balloon-letting through hole is configured for allowing therethrough a different portion of an inflated balloon-catheter balloon when the balloon-manipulating device is disposed over the balloon. Also disclosed is a balloon catheter assembly and methods of the foregoing.

Abstract: The present disclosure pertains to a system for controlling a leak flow rate during respiratory therapy. The system is configured to determine a leak flow rate necessary for CO2 expulsion for an individual subject and facilitate control of the leak flow rate during therapy such that the system exhausts substantially the entire exhaled volume of gas during an expiration of the subject. The system facilitates control of the leak flow rate during therapy via an adjustable leak valve. Determining the leak flow rate for the subject and facilitating control of the leak rate may minimize noise from air flow in the system, minimize the power draw needed by a pressure generator of the system, reduce a loss of medicine added to the respiratory therapy gas, and/or have other advantages, while still expelling the desired amount of CO2.

Abstract: Optical fiber having a coating surrounding and in direct contact with the silica based cladding region of the fiber, the coating having a Young's modulus of elasticity greater than 30 MPa. The optical fiber has low bend losses, especially low microbend induced losses. The optical fiber has a core surrounded by a cladding, and the cladding has a ring portion that includes holes or doped silica or both.

Abstract: The present invention provides a method for producing low flow rates of feedstock vapors used in the manufacture of silica glass. The method includes the steps of providing a constant flow of a liquid feedstock, mixing the flow of the liquid feedstock with an injector gas, expelling the mixture of liquid feedstock and inert gas from an injector orifice into a vaporizer chamber, flowing a carrier gas into the vaporizer chamber and through the mixture of liquid feedstock and injector gas, and vaporizing the liquid feedstock in the vaporizer chamber. The present invention is useful in the fabrication of planar silica waveguides.