Abstract: Methods and apparatuses for providing an anisotropic ion beam for etching and treatment of substrate are discussed. In one embodiment, a system for processing a substrate includes a chamber, a chuck assembly, an ion source, and a grid system. The ion source includes grid system interfaces both the chamber and the ion source and includes a plurality of holes through which ions are extracted from the ion source to form an ion beam. The grid system is oriented so the ion beam is directed into the chamber toward the substrate support, and the array of holes of the grid system is defined vertically by a y-axis and horizontally by an x-axis, The array of holes is defined by hole densities that vary vertically in the y-axis such that the ion beam is caused to have an energy density gradient that is defined vertically in the y-axis.

Abstract: A substrate processing system includes a processing chamber including a substrate support to support a substrate. A coil includes at least one terminal. An RF source configured to supply RF power to the coil. A dielectric window is arranged on one surface of the processing chamber adjacent to the coil. A contamination reducer includes a first plate that is arranged between the at least one terminal of the coil and the dielectric window.

Abstract: Methods and apparatuses for providing an anisotropic ion beam for etching and treatment of substrate are discussed. In one embodiment, a system for processing a substrate includes a chamber, a chuck assembly, an ion source, and a grid system. The ion source includes grid system interfaces both the chamber and the ion source and includes a plurality of holes through which ions are extracted from the ion source to form an ion beam. The grid system is oriented so the ion beam is directed into the chamber toward the substrate support, and the array of holes of the grid system is defined vertically by a y-axis and horizontally by an x-axis, The array of holes is defined by hole densities that vary vertically in the y-axis such that the ion beam is caused to have an energy density gradient that is defined vertically in the y-axis.

Abstract: Methods and apparatuses for providing an anisotropic ion beam for etching and treatment of substrate are discussed. In one embodiment, a system for processing a substrate includes a chamber, a chuck assembly, an ion source, and a grid system. The ion source includes grid system interfaces both the chamber and the ion source and includes a plurality of holes through which ions are extracted from the ion source to form an ion beam. The size of the plurality holes varies along an axis such that the ion density of the ion beam also varies along the axis. The density of the plurality of holes varies along an axis such that the ion density of the ion beam also varies along the axis. In some embodiments, the energies of a beamlet or multiple beamlets may be individual defined to adjust beam energy density.

Abstract: Disclosed is a wireless node with a detachable antenna. When the antenna is detached, 802.11a lower band communications are disabled. When the antenna is attached, 802.11a lower band communications are enabled.

Abstract: Disclosed is a wireless node with a detachable antenna. When the antenna is detached, 802.11a lower band communications are disabled. When the antenna is attached, 802.11a lower band communications are enabled.

Abstract: A programmable logic device (PLD) includes a fixed EXCLUSIVE OR gate and a programmable logic array (PLA). The PLA includes a plurality of AND gate and a plurality of OR gates, the output of each AND gate being programmably connected to an input of each of the plurality of OR gates. The output of one of the OR gates of the PLA array is fed to one of the inputs of the fixed EXCLUSIVE OR. Since the output of each of the AND gates is available to each of the OR gates in the PLA array, implementation of the EXCLUSIVE OR function is facilitated and the number of product terms (AND gates) required is reduced as compared to known PLDs. The output of a programmable array logic (PAL) array having a plurality of AND gates non-programmably connected to an OR gate is connected to the other one of the inputs of the fixed EXCLUSIVE OR gate.