Patents by Inventor Mark Moir

Mark Moir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8028133
    Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel and use the same shared data without causing corruption to the shared data. For example, during a commit phase, a corresponding transaction can attempt to increment a globally accessible version information variable and store a current value of the globally accessible version information variable for updating version information associated with modified data regardless of whether an associated attempt by the corresponding transaction to modify the globally accessible version information variable was successful. As an alternative mode, a corresponding transaction can merely read and store a current value of the globally accessible version information variable without attempting to update the globally accessible version information variable before such use.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: September 27, 2011
    Assignee: Oracle America, Inc.
    Inventors: David Dice, Nir N. Shavit, Ori Shalev, Mark Moir
  • Patent number: 7836228
    Abstract: A scalable first-in-first-out queue implementation adjusts to load on a host system. The scalable FIFO queue implementation is lock-free and linearizable, and scales to large numbers of threads. The FIFO queue implementation includes a central queue and an elimination structure for eliminating enqueue-dequeue operation pairs. The elimination mechanism tracks enqueue operations and/or dequeue operations and eliminates without synchronizing on the FIFO queue implementation.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: November 16, 2010
    Assignee: Oracle America, Inc.
    Inventors: Mark Moir, Ori Shalev, Nir Shavit
  • Patent number: 7640402
    Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel and use the same shared data without causing corruption to the shared data. For example, during a commit phase, a corresponding transaction can attempt to increment a globally accessible version information variable and store a current value of the globally accessible version information variable for updating version information associated with modified data regardless of whether an associated attempt by the corresponding transaction to modify the globally accessible version information variable was successful. As an alternative mode, a corresponding transaction can merely read and store a current value of the globally accessible version information variable without attempting to update the globally accessible version information variable before such use.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: December 29, 2009
    Assignee: Sun Microsystems Inc.
    Inventors: David Dice, Nir N. Shavit, Ori Shalev, Mark Moir
  • Publication number: 20080109608
    Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.
    Type: Application
    Filed: September 28, 2007
    Publication date: May 8, 2008
    Inventors: Nir Shavit, Mark Moir, Victor Luchangco
  • Publication number: 20080098181
    Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.
    Type: Application
    Filed: December 20, 2007
    Publication date: April 24, 2008
    Inventors: Mark Moir, Victor Luchangco, Maurice Herlihy
  • Publication number: 20080077748
    Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 27, 2008
    Inventors: Nir Shavit, Mark Moir, Victor Luchangco
  • Publication number: 20080077775
    Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 27, 2008
    Inventors: Nir Shavit, Mark Moir, Victor Luchangco
  • Publication number: 20080034166
    Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.
    Type: Application
    Filed: September 28, 2007
    Publication date: February 7, 2008
    Inventors: Nir Shavit, Mark Moir, Victor Lunchangeo
  • Publication number: 20070239943
    Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel and use the same shared data without causing corruption to the shared data. For example, during a commit phase, a corresponding transaction can attempt to increment a globally accessible version information variable and store a current value of the globally accessible version information variable for updating version information associated with modified data regardless of whether an associated attempt by the corresponding transaction to modify the globally accessible version information variable was successful. As an alternative mode, a corresponding transaction can merely read and store a current value of the globally accessible version information variable without attempting to update the globally accessible version information variable before such use.
    Type: Application
    Filed: January 30, 2007
    Publication date: October 11, 2007
    Inventors: David Dice, Nir N. Shavit, Ori Shalev, Mark Moir
  • Publication number: 20070186069
    Abstract: Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Software operations to modify an object may first make a private copy of the object, modify the private copy, and atomically make the private copy the current version while verifying that no other software operation or transaction has concurrently updated the object. A transaction may be used to update the current copy of a collection of data “in place” and thereby avoiding the necessity to make a copy of the data being modified. If the transactional memory mechanism is unable to complete the transaction to modify the collection of data in place, a set of software operations may be used to modify the collection of data.
    Type: Application
    Filed: March 30, 2007
    Publication date: August 9, 2007
    Inventor: Mark Moir
  • Patent number: 7251682
    Abstract: A broadcast data receiver (BDR) is provided with a web browser system. A service provided by the web browser system si selectable by a user of the BDR and, when selected, is controllable by the user via a remote control handset, thereby allowing an Internet web site page for display on a display screen connected to or forming part of the BDR to be determined and one or more user options can be selected if required. One or more icons are generated on at least a portion of the display screen and each of the icons represents a button on the remote control handset. Each icon is mapped to a specific control function or option of the web browser, thereby allowing user selection of a web browser control function or option by selection of the appropriate button on the remote control handset.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: July 31, 2007
    Assignee: Pace Micro Technology Plc
    Inventor: Mark Moir
  • Publication number: 20070174577
    Abstract: A computer system stores a dynamically sized array as a base array that contains references to subarrays in which the (composite) array's data elements reside. Each of the base-array elements that thus refers to a respective subarray is associated with a respective subarray size. Each base-array index is thereby at least implicitly associated with a cumulative base value equal to the sum of all preceding base indexes' associated subarray sizes. In response to a request for access to the element associated with a given (composite-array) index, the array-access system identifies the base index associated with the highest cumulative base value not greater than the composite-array index and performs the access to the subarray identified by the element associated with that base index. Composite-array expansion can be performed in a multi-threaded environment without locking, simply by employing a compare-and-swap or similar atomic operation.
    Type: Application
    Filed: December 18, 2006
    Publication date: July 26, 2007
    Inventors: Mark Moir, Simon Doherty
  • Publication number: 20070157202
    Abstract: One embodiment of the present invention provides a system that ensures that progress is made in an environment that supports execution of obstruction-free operations. During execution, when a process pi invokes an operation, the system checks a panic flag, which indicates whether a progress-ensuring mechanism is to be activated. If the panic flag is set, the progress-ensuring mechanism is activated, which causes the system to attempt to perform the operation by coordinating actions between processes to ensure that progress is made in spite of contention between the processes. On the other hand, if the panic flag is not set, the system attempts to perform the operation essentially as if the progress-ensuring mechanism were not present. In this case, if there is an indication that contention between processes is impeding progress, the system sets the panic flag, which causes the progress-ensuring mechanism to be activated so that processes will coordinate their actions to ensure that progress is made.
    Type: Application
    Filed: January 3, 2006
    Publication date: July 5, 2007
    Inventors: Mark Moir, Victor Luchangco, Nir Shavit
  • Publication number: 20070150509
    Abstract: In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code is prevented and all accesses to the fields of that object are performed using transactional code. In one embodiment, the current visibility of an object is stored in the object itself. This stored visibility can be checked at runtime by code that accesses the object fields or code can be generated to check the visibility prior to access during compilation.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 28, 2007
    Applicant: Sun Microsystems, Inc.
    Inventors: Yosef Lev, Jan-Willem Maessen, Mark Moir
  • Patent number: 7200854
    Abstract: The invention relates to a television or electronic program guide (EPG) of the type which is displayed on the screen of a television set to indicate channels, and programs, which are available for viewing over a time period indicated by a time bar (4). In accordance with the invention the length of the program is indicated by a cell in a displayed grid (2) and, if the program has started or will finish prior to or after the time period displayed, a display is generated which indicates to the viewer the time which has lapsed since the program started or the time remaining of the program.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: April 3, 2007
    Assignee: Pace Micro Technology Plc
    Inventor: Mark Moir
  • Publication number: 20070055960
    Abstract: Transaction code written by the programmer may be translated, replaced or transformed into a code that is configured to implement transactions according to any of various techniques. A compiler may replace programmer written transaction code into code allowing multiple compatible transaction implementation techniques to be used in the same program, and at the same time. A programmer may write transaction code once using familiar coding styles, but the transaction to be effected according to one of a number of compatible alternative implementation techniques. The compiler may enable the implementation of multiple, alternative transactional memory schemes. The particular technique implemented for each transaction may not be decided until runtime. At runtime, any of the various implemented techniques may be used to effect the transaction and if a first technique fails or is inappropriate for a particular transaction, one or more other techniques may be attempted.
    Type: Application
    Filed: November 2, 2006
    Publication date: March 8, 2007
    Applicant: Sun Microsystems, Inc.
    Inventors: Peter Damron, Yosef Lev, Mark Moir
  • Publication number: 20070043933
    Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 22, 2007
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Mark Moir, Robert Cypher, Paul Loewenstein
  • Publication number: 20070043915
    Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 22, 2007
    Applicant: Sun Microsystems, Inc.
    Inventors: Mark Moir, Robert Cypher, Paul Loewenstein
  • Publication number: 20060218561
    Abstract: A methodology has been discovered for transforming garbage collection-dependent algorithms, shared object implementations and/or concurrent software mechanisms into a form that does not presume the existence of an independent, or execution environment provided, garbage collector. Algorithms, shared object implementations and/or mechanisms designed or transformed using techniques described herein provide explicit reclamation of storage using lock-free pointer operations. Transformations can be applied to lock-free algorithms and shared object implementations and preserve lock-freedom of such algorithms and implementations. As a result, existing and future lock-free algorithms and shared object implementations that depend on a garbage-collected execution environment can be exploited in environments that do not provide garbage collection.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 28, 2006
    Inventors: Mark Moir, David Detlefs, Simon Doherty, Maurice Herlihy, Victor Luchangco, Paul Martin, Guy Steele
  • Patent number: D733681
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 7, 2015
    Inventor: Mark Moir