Abstract: An apparatus comprising a first large language model (LLM) system configured to receive a natural language specification of a system design and generate a first description of the system design in a temporal logic language responsive to the natural language specification. A second LLM system is configured to receive the natural language specification and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM is configured to generate verification drivers for the system design responsive to the first description of the system design. A formal verification (FV) tool is configured to indicate whether the system design passes or fails responsive to the first description of the system design in a temporal logic language.

Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A first finite state machine (FSM) is configured to generate verification properties for the system design responsive to the first description of the system design in the temporal logic language. A second FSM configured to generate verification drivers for the system design. A formal verification (FV) tool configured to determine whether a model of the system design passes or fails. The FV tool is further configured to generate a property witness template and an optimal witness template.

Abstract: An apparatus for performing formal verification of a system design comprises a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language. A second LLM system is configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A generator and compiler is configured to generate finite state machines. At least one finite state machine (FSM) generated by the generator and compiler is configured to analyze operation of the system design using each of the at least one FSM including optimization properties. A formal verification (FV) tool is configured to determine whether the system design passes or fails responsive to the first description of the system design in the temporal logic language.

Abstract: An apparatus for performing formal verification of a system design, comprising a first large language model (LLM) system configured to receive a natural language specification of the system design and generate a first description of the system design in a temporal logic language and a second LLM system configured to receive the natural language specification of the system design and generate a second description of the system design in the temporal logic language. A finite state machine (FSM) is configured to verify the system design responsive to the second description of the system design in the temporal logic. A formal verification (FV) tool is configured to indicate whether the system design passes or fails, wherein the FV tool is further configured to provide a verification coverage estimation of a model implemented by the FV tool using a finite elements method (FEM) triangulation mesh.