Abstract: A method of equalizing charge states of individual cells in a battery includes measuring a previous cell voltage for each cell, measuring a previous shunt current for each cell, calculating, based on the previous cell voltage and the previous shunt current, an adjusted cell voltage for each cell, determining a lowest adjusted cell voltage from among the calculated adjusted cell voltages, and calculating a new shunt current for each cell.

Abstract: A method of equalizing charge states of individual cells in a battery includes measuring a previous cell voltage for each cell, measuring a previous shunt current for each cell, calculating, based on the previous cell voltage and the previous shunt current, an adjusted cell voltage for each cell, determining a lowest adjusted cell voltage from among the calculated adjusted cell voltages, and calculating a new shunt current for each cell.

Abstract: A method and structure for minimizing one or more non-uniformities in image and position sensing detectors are provided. The structure is directed to a focal plane processor for removing non-uniformities which distort the computation of a desired property of an object of interest in an image field. The focal plane processor is capable of selectively disconnecting one or more rows and/or columns from further processing in the imaging array for those rows and/or columns which contribute to the presence of at least one non-uniformity in a video image generated by the focal plane processor. In one embodiment, the disconnection means is embodied as pre-processing circuitry which includes row and column shift registers which provide control signals to area-of-interest (AOI) switches. In another embodiment, the pixels which comprise the focal plane array are constructed in a manner which facilitates their individual isolation.

Abstract: A process for fabricating a semiconductor device having, for example, a MISFET transistor, is provided which comprises the steps of (a) providing a partially fabricated semiconductor device comprising a substrate and a first and second polysilican layer insulatively spaced from the substrate by an insulating layer, the insulating layer having an opening therein which exposes the surface of the first polysilicon layer positioned below the second polysilicon layer and (b) exposing the partially fabricated semiconductor device to a noble gas halide to substantially remove the first polysilicon layer.

Abstract: A metal oxide semiconductor field effect transistor (“MOSFET”) layout with small width-length ratio allows for greater flexibility in design and density in dimension than the conventional annular technique is provided. Accordingly, higher density MOSFET of this layout gives more devices on a single semiconductor wafer. An additional benefit of this layout is a reduced current density at the enclosed terminal wherein there is less localized heating and damages of materials composing the transistor.

Abstract: A method and structure for minimizing one or more non-uniformities in image and position sensing detectors are provided. The structure is directed to a focal plane processor for removing non-uniformities which distort the computation of a de-sired property of an object of interest in an image field. The focal plane processor is capable of selectively disconnecting one or more rows and/or columns from further processing in the imaging array for those rows and/or columns which contribute to the presence of at least one non-uniformity in a video image generated by the focal plane processor. In one embodiment, the disconnection means is embodied as pre-processing circuitry which includes row and column shift registers which provide control signals to area-of-interest (AOI) switches. In another embodiment, the pixels which comprise the focal plane array are constructed in a manner which facilitates their individual isolation.

Abstract: A process for fabricating a semiconductor device having, for example, a MISFET transistor, is provided which comprises the steps of (a) providing a partially fabricated semiconductor device comprising a substrate and a first and second polysilicon layer insulatively spaced from the substrate by an insulating layer, the insulating layer having an opening therein which exposes the surface of the first polysilicon layer positioned below the second polysilicon layer and (b) exposing the partially fabricated semiconductor device to a noble gas halide to substantially remove the first polysilicon layer.