Patents by Inventor Mark Nakamoto

Mark Nakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110221053
    Abstract: A method for packaging a stacked integrated circuit (IC) includes pre-processing the stacked IC before releasing the stacked IC from the carrier wafer. Pre-processing reduces wafer warpage and simplifies the packaging process by dicing materials separately. Pre-processing may be performed on the first tier wafer of a stacked IC during manufacturing to partially or completely dice the first tier wafer into first tier dies before release from the carrier wafer. Pre-processing may also be performed by laser cutting the mold compound surrounding the first tier wafer and second tier dies before releasing the stacked IC from the carrier wafer. Openings in the first tier wafer and/or mold compound allows balancing of stresses in the packaging process and reduction of wafer warpage.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Arvind Chandrasekaran, Mark Nakamoto