Patents by Inventor Mark Nightingale
Mark Nightingale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11556960Abstract: Methods and apparatus to deliver targeted advertising are disclosed. An example apparatus includes processor circuitry to: obtain user behavior information corresponding to interaction with a first media object from a user, the first media object including a first customizable media object element and a second customizable media object element independent of the first customizable media object element; analyze a performance of the first media object based on the user behavior information; and update at least one of a user profile of the user or a group profile corresponding to the user using a machine learning model to adjust ratings of the first customizable media object element and the second customizable media object element based on a comparison of the performance of the first media object to a second custom object including at least one of the first customizable media object element or the second customizable media object element.Type: GrantFiled: August 2, 2021Date of Patent: January 17, 2023Assignee: The Nielsen Company (US), LLCInventors: Aaron Mark Nightingale, Juan Carlos Garcia Bazan
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Publication number: 20220036406Abstract: Methods and apparatus to deliver targeted advertising are disclosed. An example apparatus includes processor circuitry to: obtain user behavior information corresponding to interaction with a first media object from a user, the first media object including a first customizable media object element and a second customizable media object element independent of the first customizable media object element; analyze a performance of the first media object based on the user behavior information; and update at least one of a user profile of the user or a group profile corresponding to the user using a machine learning model to adjust ratings of the first customizable media object element and the second customizable media object element based on a comparison of the performance of the first media object to a second custom object including at least one of the first customizable media object element or the second customizable media object element.Type: ApplicationFiled: August 2, 2021Publication date: February 3, 2022Inventors: Aaron Mark Nightingale, Juan Carlos Garcia Bazan
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Patent number: 11080756Abstract: Methods and apparatus to deliver targeted advertising are disclosed. An example apparatus includes a media object assembler to, in response to receiving a request to provide a media object, generate a custom media object using a first media object element and a second media object element based on at least one of a user profile or a group profile corresponding to a user, the user corresponding to the request; an interface to transmit the custom media object to the user; and a performance analyzer to analyze a performance of the custom media object; and update at least one of the user profile or the group profile based on the performance.Type: GrantFiled: July 28, 2017Date of Patent: August 3, 2021Assignee: THE NIELSEN COMPANY (US), LLCInventors: Aaron Mark Nightingale, Juan Carlos Garcia Bazan
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Publication number: 20180137540Abstract: Methods and apparatus to deliver targeted advertising are disclosed. An example apparatus includes a media object assembler to, in response to receiving a request to provide a media object, generate a custom media object using a first media object element and a second media object element based on at least one of a user profile or a group profile corresponding to a user, the user corresponding to the request; an interface to transmit the custom media object to the user; and a performance analyzer to analyze a performance of the custom media object; and update at least one of the user profile or the group profile based on the performance.Type: ApplicationFiled: July 28, 2017Publication date: May 17, 2018Inventors: Aaron Mark Nightingale, Juan Carlos Garcia Bazan
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Patent number: 8180620Abstract: Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding portion of the system under verification and the signal interface controller during verification. A debugger controls an associated processing unit that executes software routines. A debugger signal interface controller performs test actions transferring stimulus signals and response signals between the debugger and the debugger signal interface controller during verification. A test manager transfers test controlling messages to these interface controllers identifying the test actions to be performed. As a result, the test manager controls the processing unit via the debugger signal interface controller and the debugger in order to coordinate the execution of the software routines with a sequence of verification tests.Type: GrantFiled: January 27, 2004Date of Patent: May 15, 2012Assignee: ARM LimitedInventor: Andrew Mark Nightingale
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Patent number: 7979822Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.Type: GrantFiled: June 3, 2008Date of Patent: July 12, 2011Assignee: ARM LimitedInventors: Andrew Mark Nightingale, Louise Margaret Jameson
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Patent number: 7856346Abstract: A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.Type: GrantFiled: May 10, 2002Date of Patent: December 21, 2010Assignee: ARM LimitedInventors: Andrew Mark Nightingale, Timothy Charles Mace
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Patent number: 7761280Abstract: Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.Type: GrantFiled: March 17, 2004Date of Patent: July 20, 2010Assignee: ARM LimitedInventors: Andrew Mark Nightingale, Daren Croxford
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Patent number: 7627462Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.Type: GrantFiled: November 27, 2001Date of Patent: December 1, 2009Assignee: ARM LimitedInventor: Andrew Mark Nightingale
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Publication number: 20090070493Abstract: A method of generating a configuration of an integrated circuit 2 having an interconnect component 14 connecting a plurality of devices 4, 6, 8, 10, 12 uses selecting a device to be connected to the interconnect component, reading interface parameters of that device from a file or model (e.g. IP-XACT), selecting parameters of an interface “if” of the interconnect component to match the read parameters, detecting and making any settings in the configuration of the interconnect component 14 itself required to match the selected parameters of the interface and then detecting any changes required in the configuration of any devices previously connected to the interconnect component required to match the configuration of the interconnect component as it now stands. In this way, configuration of the interconnect component can be at least semi-automated with a reduction in the possibility of errors and an increase in the speed of such configuration.Type: ApplicationFiled: August 8, 2008Publication date: March 12, 2009Applicant: ARM LIMITEDInventors: Peter Andrew Riocreux, Andrew Mark Nightingale
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Publication number: 20080313587Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.Type: ApplicationFiled: June 3, 2008Publication date: December 18, 2008Applicant: ARM LIMITEDInventors: Andrew Mark Nightingale, Louise Margaret Jameson
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Patent number: 7366650Abstract: A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.Type: GrantFiled: February 22, 2002Date of Patent: April 29, 2008Assignee: ARM LimitedInventors: Andrew Mark Nightingale, Alistair Crone Bruce
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Publication number: 20070257025Abstract: A probe comprises a small “consumable” probe substrate permanently mounted to a circuit-under-test. The probe substrate includes a high-fidelity signal pathway, which is inserted into a conductor of the circuit-under-test, and a high-bandwidth sensing circuit which senses the signal-under-test as it propagates along the signal pathway. The probe substrate further includes a probe socket for receiving a detachable interconnect to a measurement instrument. Power is alternatively supplied to the probe by the circuit-under-test or the interconnect. When the interconnect is attached, control signals from the measurement instrument are supplied to the sensing circuit and the output of the sensing circuit is supplied to the measurement instrument. In one embodiment, the sensing circuit uses high-breakdown transistors in order to avoid the use of passive attenuation. In a further embodiment, the sensing circuit includes broadband directional sensing circuitry.Type: ApplicationFiled: May 4, 2006Publication date: November 8, 2007Inventors: Robert Nordstrom, William Law, Mark Nightingale, Einar Traa, Ira Pollock
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Publication number: 20070159195Abstract: A differential measurement probe has a ground clip system for electrically coupling outer shielding conductors of differential probing tips together. In one embodiment, the probing tips independently move vertically relative to each other with the ground clip system secured to each of the outer shielding conductors of the probing tips. In a further embodiment, the probing tips move both vertically and horizontally and the ground clip system has a spring wire member that is secured to the probe. The spring wire member is formed with various sections having various angles to each other that allows one section to slidably engage one of the outer shielding conductors on one of the probing tips and another section to slidably engage the outer shielding conductor of the other probing tip.Type: ApplicationFiled: March 21, 2007Publication date: July 12, 2007Applicant: TEKTRONIX, INC.Inventors: Kei-Wean Yang, Mark Nightingale, Paul Chastain
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Publication number: 20060267605Abstract: A differential measurement probe has a ground clip system for electrically coupling outer shielding conductors of differential probing tips together. In one embodiment, the probing tips independently move vertically relative to each other with the ground clip system secured to each of the outer shielding conductors of the probing tips. In a further embodiment, the probing tips move both vertically and horizontally and the ground clip system has a spring wire member that is secured to the probe. The spring wire member is formed with various sections having various angles to each other that allows one section to slidably engage one of the outer shielding conductors on one of the probing tips and another section to slidably engage the outer shielding conductor of the other probing tip.Type: ApplicationFiled: May 27, 2005Publication date: November 30, 2006Inventors: Kei-Wean Yang, Mark Nightingale, Paul Chastain
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Publication number: 20060267602Abstract: A signal acquisition probe has a double cushioned spring loaded probing tip assembly disposed in a housing. A first compressive element produces a first pre-loaded compressive force and an increasing compressive force on the probing tip assembly and a second compressive element produces a second pre-loaded compressive force and an increasing compressive force on the probing tip assembly subsequent to the first increasing compressive force. First and second double cushioned spring loaded probing tip assemblies may be disposed in a housing to produce a differential signal acquisition probe.Type: ApplicationFiled: May 27, 2005Publication date: November 30, 2006Inventors: Kei-Wean Yang, Mark Nightingale
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Patent number: 7099813Abstract: A simulation system is provided for simulating operation of a plurality of hardware devices in combination with an instruction set simulator simulating execution of program instructions by a program core. A test scenario manager acts as a master and serves to command the hardware devices and the instruction set simulator with stimulus signals to simulate various specified activity.Type: GrantFiled: April 9, 2002Date of Patent: August 29, 2006Assignee: ARM LimitedInventor: Andrew Mark Nightingale
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Publication number: 20050263317Abstract: An inverted strain relief for receiving a coaxial cable has a housing with a bore therethrough defining first and second apertures in opposing surfaces of the housing. The bore surface is defined by at least a first radius scribing an arc from the perimeter of the first aperture to the second aperture. A smaller second radius scribes an arc tangential to the arc of the first radius over a portion of the exterior surface of the housing. Alternately, the first and second radii may define the surface of the bore with the second radius extending over a portion of the exterior surface of the housing. The bore in the housing is definable by an additional aperture formed adjacent to the first aperture. The surface of the bore is defined by at least the first radius extending from the perimeters of the adjacent apertures.Type: ApplicationFiled: May 27, 2004Publication date: December 1, 2005Inventor: Mark Nightingale
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Patent number: 6876941Abstract: The present invention provides a system and method for testing compliance of a device with a bus protocol. The method comprises the steps of reading a configuration file containing predetermined parameters identifying the type of device and capabilities of the device, and then employing a configuration engine to dynamically generate a test environment for the device by creating selected test components which are coupled via the bus with a representation of the device to form the test environment, the test components being selected dependent on the configuration file. A test sequence is then executed, during which signals passed between the representation of the device and one or more of the test components are monitored to generate result data indicating compliance with the bus protocol. This approach has been found to provide a particularly user friendly and efficient approach for testing compliance of devices with a bus protocol.Type: GrantFiled: February 28, 2002Date of Patent: April 5, 2005Assignee: Arm LimitedInventor: Andrew Mark Nightingale
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Publication number: 20030212968Abstract: A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.Type: ApplicationFiled: May 10, 2002Publication date: November 13, 2003Inventors: Andrew Mark Nightingale, Timothy Charles Mace