Abstract: This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.