Abstract: A system and method for partitioning processor resources based on memory usage is provided. A compiler determines the extent to which a process is memory-bound and accordingly divides the process into a number of threads. When a first thread encounters a prolonged instruction, the compiler inserts a conditional branch to a second thread. When the second thread encounters a prolonged instruction, a conditional branch to a third thread is executed. This continues until the last thread conditionally branches back to the first thread. An indirect segmented register file is used so that the “return to” and “branch to” logical registers within each thread are the same (e.g., R1 and R2) for each thread. These logical registers are mapped to hardware registers that store actual addresses. The indirect mapping is altered to bypass completed threads. When the last thread completes it may signal an external process.

Abstract: The present invention provides for notifying threads. A determination is made whether there is a condition for which a thread is to be notified. If so, a notification indicia is broadcasted. A flag is set in at least one memory storage area as a function of the notification indicia wherein the setting the flag occurs without the intervention of an operating system. Therefore, latencies for notification of threads are minimized.

Abstract: A System and method for hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.

Abstract: A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, regardless of whether the processor is running. Additional threads create additional local memory mappings into the effective address space. The effective address space corresponds to either a physical local memory or a “soft” copy area. When the processor is running, a different processor may access data that is located in the first processor's local memory from the processor's local storage area. When the processor is not running, a softcopy of the processor's local memory is stored in a memory location (i.e. locked cache memory, pinned system memory, virtual memory, etc.) for other processors to continue accessing.

Abstract: A system and method for sharing resources between real-time and virtualizing operating systems is presented. A computer system uses effective address mapping of support processors' local memory to share resources between separate operating systems. When threads are created for either operating system, the thread's corresponding processor memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by the thread, regardless of whether the processor is running, or whether the processor is executing a different thread from a different operating system. For example, a computer system may have eight support processors and running two operating systems whereby the first operating system requires six support processors and the second operating system requires all eight support processors. In this example, resources are virtualized and shared between the two operating systems in order to meet the requirements of both operating systems.

Abstract: A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. The main processor then determines whether a kernel or an application should process the interrupt. Interrupts such as page faults, segment faults, and alignment errors are handled by the kernel, while “informational” signals, such as stop and signal requests, halt requests, mailbox requests, and DMC tag complete requests are handled by the application. In addition, multiple identical events are maintained, and event data may be included in the interrupt using the invention described herein.

Abstract: An apparatus, a method, and a computer program product are provided for more efficiently allowing context switching. Currently, context switching can be costly because of both memory requirements to store data from pre-empted applications, as well as the bus requirements to move the data at pre-emption. To alleviate at least some of the costs associated with context switching, addition fields, either with associated Application Program Interfaces (APIs) or coupled to application modules, can be employed to indicate points of light weight context during the operation of an application. Therefore, an operating system can pre-empt applications at points where the context is relatively light, reducing the costs on both storage and on bus usage.

Abstract: A system and method for terrain rendering using a limited memory footprint is presented. A system and method to perform vertical ray terrain rendering by using a terrain data subset for image point value calculations. Terrain data is segmented into terrain data subsets whereby the terrain data subsets are processed in parallel. A bottom view ray intersects the terrain data to provide a memory footprint starting point. In addition, environmental visibility settings provide a memory footprint ending point. The memory footprint starting point, the memory footprint ending point, and vertical ray adjacent data points define a terrain data subset that corresponds to a particular vertical ray. The terrain data subset includes height and color information which are used for vertical ray coherence terrain rendering.

Abstract: A warm-up bat includes a tubular shell with a handle section, a barrel section, and a tapered section connecting the handle section with the barrel section. The handle is attached at an end of the handle section of the bat. An end cap is attached at an end of the barrel section of the bat. A sliding weight mechanism is entirely contained within the barrel section of the bat, and is positionally supported on a shaft.

Abstract: A method and a system for managing a computer system's multiple processors as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Abstract: A system and method for loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.

Abstract: A system and method for balancing computational load across a plurality of processors. Source code subtasks are compiled into byte code subtasks whereby the byte code subtasks are translated into processor-specific object code subtasks at runtime. The processor-type selection is based upon one of three approaches which are 1) a brute force approach, 2) higher-level approach, or 3) processor availability approach. Each object code subtask is loaded in a corresponding processor type for execution. In one embodiment, a compiler stores a pointer in a byte code file that references the location of a byte code subtask. In this embodiment, the byte code subtask is stored in a shared library and, at runtime, a runtime loader uses the pointer to identify the location of the byte code subtask in order to translate the byte code subtask.

Abstract: A system and method for an asymmetric heterogeneous multi-threaded operating system are presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.

Abstract: A system and method for grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.

Abstract: A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.

Abstract: A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.

Abstract: A system and method for a processor thread acting as a system service provider is presented. A computer system boots up and initiates a service thread. The service thread is responsible for service related tasks, such as ECC checks and hardware log error checks. The service provider invokes a second thread which is used as an operational thread. The operational thread loads an operating system, a kernel, and runs various applications. While the operational thread executes, the service thread monitors the operational thread for proper functionality as well as monitoring service events. When the service thread detects a problem with either one of the service events or the operational thread, the service thread may choose to store operational data corresponding to the operational thread and terminates the operational thread.

Abstract: A method and system for solving a large system of dense linear equations using a system having a processing unit and one or more secondary processing units that can access a common memory for sharing data. A set of coefficients corresponding to a system of linear equations is received, and the coefficients, after being placed in matrix form, are divided into blocks and loaded into the common memory. Each of the processors is programmed to perform matrix operations on individual blocks to solve the linear equations. A table containing a list of the matrix operations is created in the common memory to keep track of the operations that have been performed and the operations that are still pending. SPUs determine whether tasks are pending, access the coefficients by accessing the common memory, perform the required, and store the result back in the common memory for the result to be accessible by the PU and the other SPUs.

Abstract: A system and method is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.

Abstract: A system and method is provided to perform code handling, such as interpreting language instructions or performing “just-in-time” compilation using a heterogeneous processing environment that shares a common memory. In a heterogeneous processing environment that includes a plurality of processors, one of the processors is programmed to perform a dedicated code-handling task, such as perform just-in-time compilation or interpretation of interpreted language instructions, such as Java. The other processors request code handling processing that is performed by the dedicated processor. Speed is achieved using a shared memory map so that the dedicated processor can quickly retrieve data provided by one of the other processors.