Abstract: The invention provides an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or outer further comprises an encapsulator connected to receive Ethernet Protocol Data Units from the Ethernet ports, wherein the encapsulator is operable to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit. Also provided is a method of data delivery across a network.

Abstract: A switch device for use in telecommunications apparatus, the switch device comprising: a substantially planar substrate having first substantially planar face and an opposing second substantially planar face; a first plurality of ports mounted on the first face of the substrate, and having a first arrangement of locating pins which extend into the substrate from the first face towards the second face thereof; and a second plurality of ports mounted on the second face of the substrate, and having a second arrangement of locating pins which extend into the substrate from the second face towards the first face thereof, wherein the first arrangement of locating pins is offset with respect to the second arrangement of locating pins.

Abstract: The invention provides an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises an encapsulator connected to receive Ethernet Protocol Data Units from the Ethernet ports, wherein the encapsulator is operable to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit. Also provided is a method of data delivery across a network.

Abstract: The present invention provides a multi-path network for use in a bridge, switch, router, hub or the like, comprising a plurality of network ports adapted for connection with one or more devices, each device having a different identifying address data; a plurality of network elements; and a plurality of network links interconnecting the network elements and connecting the network elements to the network ports, wherein the multi-path network further comprises separately addressable memory elements each adapted for storing device address data and the multi-path network is adapted to distribute a plurality of device address data amongst the plurality of memory elements.

Abstract: A switch device for use in telecommunications apparatus, the switch device comprising: a substantially planar substrate having first substantially planar face and an opposing second substantially planar face; a first plurality of ports mounted on the first face of the substrate, and having a first arrangement of locating pins which extend into the substrate from the first face towards the second face thereof; and a second plurality of ports mounted on the second face of the substrate, and having a second arrangement of locating pins which extend into the substrate from the second face towards the first face thereof, wherein the first arrangement of locating pins is offset with respect to the second arrangement of locating pins.

Abstract: The invention provides an Ethernet bridge or router comprising a network fabric adapted to provide interconnectivity to a plurality of Ethernet ports, each of the Ethernet ports being adapted to receive and/or transmit Ethernet frames, and wherein the Ethernet bridge or router further comprises an encapsulator connected to receive Ethernet Protocol Data Units from the Ethernet ports, wherein the encapsulator is operable to generate a Fabric Protocol Data Unit from a received Ethernet Protocol Data Unit, the Fabric Protocol Data Unit comprising a header portion, and a payload portion which comprises the Ethernet Protocol Data Unit concerned, and wherein the encapsulator is operable to transform Ethernet destination address information from the Ethernet Protocol Data Unit into a routing definition for the network fabric, and to include this routing definition in the header portion of the Fabric Protocol Data Unit. Also provided is a method of data delivery across a network.

Abstract: The present invention provides a multi-path network for use in a bridge, switch, router, hub or the like, comprising a plurality of network ports adapted for connection with one or more devices, each device having a different identifying address data; a plurality of network elements; and a plurality of network links interconnecting the network elements and connecting the network elements to the network ports, wherein the multi-path network further comprises separately addressable memory elements each adapted for storing device address data and the multi-path network is adapted to distribute a plurality of device address data amongst the plurality of memory elements.

Abstract: A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract: There is described a cache memory system including a first cache memory and a second cache memory. A first port is arranged to receive a request for a first item and determine whether the first item is in the first cache memory. A second port is arranged to receive a request for a second item and determine whether the second item is in the second cache memory. The system is arranged such that if the second item is determined not to be in the second cache memory, a request for the second item is sent to the first port. There is also described a method of accessing multiple items from a memory which has associated with it a first cache memory having a first port and a second cache memory having a second port.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.

Abstract: There is disclosed a data processor containing an instruction issue unit that efficiently transfers instruction bundles from a cache to an instruction pipeline. The data processor comprises 1) an instruction pipeline comprising N processing stages; and 2) an instruction issue unit for fetching into the instruction pipeline instructions fetched from the instruction cache, each of the fetched instructions comprising from one to S syllables.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: There is described a cache memory system including a first cache memory and a second cache memory. A first port is arranged to receive a request for a first item and determine whether the first item is in the first cache memory. A second port is arranged to receive a request for a second item and determine whether the second item is in the second cache memory. The system is arranged such that if the second item is determined not to be in the second cache memory, a request for the second item is sent to the first port. There is also described a method of accessing multiple items from a memory which has associated with it a first cache memory having a first port and a second cache memory having a second port.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t0, and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t0.

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The power-down controller monitors the instruction cache and each instruction execution pipeline to identify power-down conditions associated with the same and, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of the N processing stages associated with an executing instruction, (ii) powers down the instruction cache, and (iii) powers down the data processor.