Patents by Inventor Mark Owen Maxson

Mark Owen Maxson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7074050
    Abstract: A socket assembly with incorporated memory structure is provided. A chip carrier socket assembly includes dual stage clamping actuation. A first clamping actuation stage provides clamping force for ball grid array (BGA) contact pads and a second clamping actuation stage provides clamping force for a thermal interface. The first clamping actuation stage provides clamping force proximate to a perimeter of a carrier where a plurality of BGA contact pads are located. The second clamping actuation stage provides clamping force generally centrally of the chip carrier socket assembly for thermal interface actuation.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: July 11, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Patent number: 7050871
    Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: May 23, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson, John Edward Sheets, II
  • Patent number: 7036709
    Abstract: A method and structure are provided for implementing a column attach coupled noise suppressor for a solder column structure of the type used to join a substrate to a circuit card. The electrical noise suppressor structure includes a plurality of elongated through openings that are arranged in a predefined pattern. The elongated through openings have electrically conductive sidewalls and are electrically connected together. The predefined pattern of the elongated, electrically conductive through openings corresponds to a layout of solder columns. The solder columns are attached at one end to either a substrate or a circuit card and are inserted through the elongated through openings of the electrical noise suppressor structure, spaced apart from the electrically conductive sidewalls. Then the solder columns are attached at the other end to the other one of the substrate or circuit card.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Patent number: 7036710
    Abstract: A method and structures are provided for implementing an impedance-controlled coupled noise suppressor for a differential interface solder column array used to join a substrate to a circuit card. The impedance-controlled coupled noise suppressor structure includes a plurality of elongated through openings that are arranged in a predefined pattern with one or more of the through openings receiving a differential signal pair of solder columns. The elongated through openings have electrically conductive sidewalls and are electrically connected together. The predefined pattern of the elongated, electrically conductive through openings corresponds to a layout of solder columns. The solder columns are attached at opposite ends to a substrate and a circuit card. An electrical connection is provided between the impedance-controlled coupled noise suppressor structure and an image return current path of the circuit card.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Publication number: 20060087379
    Abstract: A method and structure are provided to control common mode impedance in fan-out regions for printed circuit board applications. A differential pair transmission line includes a narrow signal trace portion in the fan-out region and a wider signal trace portion outside of the fan-out region. A dielectric material separates the differential pair transmission line from a reference power plane. A thickness of the narrow signal trace is increased and a thickness of the dielectric material is correspondingly decreased in the fan-out region.
    Type: Application
    Filed: October 21, 2004
    Publication date: April 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Maki, Mark Owen Maxson
  • Patent number: 7010768
    Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Paul Eric Dahlen, Roger John Gravrok, David Loren Heckmann, Mark Owen Maxson
  • Patent number: 6998852
    Abstract: A method and apparatus are provided for implementing direct attenuation loss measurement in an electronic package. A sinusoidal voltage source signal of a selected frequency is coupled to an embedded transmission line test structure in the electronic package. Receive circuitry is coupled to the transmission line test structure for detecting amplitude of a received sinusoidal voltage source signal to identify attenuation loss through the transmission line test structure. An identified attenuation loss of the transmission line test structure is compared with a threshold value for verifying acceptable attenuation of the electronic package transmission line test structure.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Patent number: 6987397
    Abstract: A method and a probe structure are provided for implementing multiple signals probing of a printed circuit board. A probe structure is formed on an outside surface of the printed circuit board. A resistor is electrically connected with an associated via with a signal to be monitored. A path to a predefined probe location for monitoring the signal is defined from the resistor using the probe structure.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Patent number: 6956383
    Abstract: A method and apparatus are provided for implementing automated electronic package transmission line characteristic impedance verification. A sinusoidal voltage source is coupled to a transmission line test structure for generating a selected frequency. Impedance measuring circuitry is coupled to the transmission line test structure for measuring an input impedance with an open-circuit termination and a short-circuit termination. Characteristic impedance calculation circuitry is coupled to the impedance measuring circuitry receiving the input impedance measured values for the open-circuit termination and the short-circuit termination for calculating characteristic impedance. Logic circuitry is coupled to the characteristic impedance calculation circuitry for comparing the calculated characteristic impedance with threshold values for verifying acceptable electronic package transmission line characteristic impedance.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Publication number: 20050192691
    Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Maki, Mark Owen Maxson, John Edward Sheets
  • Publication number: 20040261045
    Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.
    Type: Application
    Filed: June 17, 2003
    Publication date: December 23, 2004
    Applicant: INTERNATIONAL BUSSINESS MACHINES CORPORATION
    Inventors: Paul Eric Dahlen, Roger John Gravrok, David Loren Heckmann, Mark Owen Maxson
  • Publication number: 20040251047
    Abstract: Methods and apparatus are disclosed for improved via utilization on printed wiring boards (PWB). A via in a PWB typically transfers a single electrical signal from one signal plane to another wiring plane on the PWB. The present invention provides for more than a single signal to be transferred through a single via having a conducting wall. The conducting wall of the via is divided into more than one conducting portion, each portion capable of conducting a signal from one signal plane to another signal plane.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Publication number: 20040189418
    Abstract: A method and structure are provided for implementing enhanced differential signal trace routing in a printed circuit board. The structure includes a differential signal trace pair and a differential pair via arrangement including a pair of vias. The pair of vias is coupled to the differential signal trace pair for routing the differential signal trace pair between first and second layers of the PCB. The vias are laterally offset by a predefined spacing sharing overlapping clearance holes and are diagonally oriented to allow minimal separation of the differential signal trace pair and matched signal trace lengths of the differential signal trace pair.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald Keith Bartley, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson
  • Patent number: 6757175
    Abstract: A method and embedded bus bar structure are provided for implementing power distribution in an electronic system. A stiffener includes an embedded power bus bar structure for distributing power. The embedded power bus bar structure has a predefined pattern within a selected area of the stiffener. The selected area is separated from at least one predefined area. A printed circuit board is mounted to the stiffener and electrically connected to the embedded power bus bar structure. The embedded power bus bar structure can include multiple spaced apart power bus bars, enabling the power distribution of multiple voltage levels. The predefined pattern of the embedded power bus bar structure within the selected area of the stiffener is separated from each predefined site for a Land Grid Array (LGA).
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: June 29, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Paul Eric Dahlen, Philip Raymond Germann, Andrew B. Maki, Mark Owen Maxson