Abstract: The present invention beneficially provides a method and apparatus for cross-referencing graphical objects and hardware description language (HDL) statements. According to one aspect of the present invention, a cross-referencing record is automatically generated to map graphical objects to corresponding HDL statements. According to a second aspect of the invention, a request is received to cross-reference a HDL statement and a graphical object. Based on the request, the cross-referencing record is accessed to identify a target of the request.

Abstract: An integrated circuit having a built-in self test facility, the integrated circuit being partitioned into a number of sub-circuits each of which comprises a combinatorial logic circuit and a register. The sub-circuits are coupled together so that each combinatorial logic circuit has its inputs coupled to at least one register, has its outputs coupled to at least one register, and the output of the overall integrated circuit is taken from one or more registers. Each register has its fucntional mode controlled by predetermined signals to an associated local decoder, the functional modes of the registers being selected to initiate a test operation for the testing of the integrated circuit.

Abstract: A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates coupled to a flip-flop via a third gate. The present invention provides a multiplexer coupled to one input of the first gate, the multiplexer being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate and a fourth gate coupled to an input of the second gate, the fourth gate having an input connected to receive a signal dependent on the control signal to the data selector means.

Abstract: An integrated circuit having a built-in self test design, the integrated circuit including a combinatorial logic circuit, a first register coupled to an output of the combinatorial logic circuit and a feedback path via which output signals from the first register are fed back to an input of the combinatorial logic circuit. A multiplexer is provided between the first register and the feedback path, and there is also provided a second register responsive to a signal which is originated to initiate a test function for feeding test signals via the multiplexer and the feedback path to the input of the combinatorial logic circuit.