Abstract: A planar electronic device includes a planar substrate having a cavity configured to receive a ferrite material body therein. The planar substrate has an upper side and a lower side and conductive vias extending through the substrate. Top conductors are provided on the upper side of the planar substrate and are electrically connected to corresponding conductive vias. Bottom conductors are provided on the lower side of the planar substrate and are electrically connected to corresponding conductive vias. The bottom conductors, top conductors and conductive vias define a primary conductive loop and a secondary conductive loop. An upper cover layer covers the upper side and has a high permittivity. The upper cover layer is positioned relative to the top conductors to increase capacitance between the primary and secondary loops.

Abstract: A planar electronic device includes top conductors on a top side of a planar substrate connected to conductive vias and defining top conductor groups and bottom conductors on a bottom side connected to corresponding vias and defining bottom conductor groups. The conductors and vias define primary and secondary conductive loops with the top conductor group including at least one primary top conductor and at least one secondary top conductor and with the bottom conductor group including at least one primary bottom conductor and at least one secondary bottom conductor. The top conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups, and the bottom conductors within each group have substantially similar layouts that are different from layouts of the immediately adjacent groups.

Abstract: A planar electronic device includes a planar substrate having a cavity configured to receive a ferrite material body therein. The planar substrate has an upper side and a lower side and conductive vias extending through the substrate. Top conductors are provided on the upper side of the planar substrate and are electrically connected to corresponding conductive vias. Bottom conductors are provided on the lower side of the planar substrate and are electrically connected to corresponding conductive vias. The bottom conductors, top conductors and conductive vias define a primary conductive loop and a secondary conductive loop. An upper cover layer covers the upper side and has a high permittivity. The upper cover layer is positioned relative to the top conductors to increase capacitance between the primary and secondary loops.