Abstract: There is provided a method of discrete optimisation comprising: receiving an optimisation objective function; performing a continuous optimisation based upon the optimisation objective function to generate an initial continuous value; generating a plurality of candidate discrete values based upon the initial continuous value; evaluating the plurality of candidate discrete values based upon the optimisation objective function, wherein the evaluation of the plurality of candidate discrete values is carried out in parallel; and outputting a candidate discrete value based upon the evaluation.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Abstract: There is provided a method of discrete optimisation comprising: receiving an optimisation objective function; performing a continuous optimisation based upon the optimisation objective function to generate an initial continuous value; generating a plurality of candidate discrete values based upon the initial continuous value; evaluating the plurality of candidate discrete values based upon the optimisation objective function, wherein the evaluation of the plurality of candidate discrete values is carried out in parallel; and outputting a candidate discrete value based upon the evaluation.

Abstract: Methods and systems of optimization constraint adaptation for long-term target achievement. One system includes an electronic processor configured to divide a multiple time-step optimization problem into a plurality of successive single time-step optimization problems. The processor is configured to determine a first optimal variable value for a first single time-step optimization problem and determine a first resulting value of a secondary quantity based on the first optimal variable value. The processor is configured to determine a first divergence of the first resulting value from a first target value and determine a cumulative target divergence based on the first divergence. The processor is configured to determine a first target value adjustment for a second time-step based on the cumulative target divergence, adjust a first original target value of the secondary quantity for the second time-step using the first target value adjustment, and output the adjusted first original target value for display.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.

Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Abstract: The present invention provides a novel method for protein manufacture wherein the protein is expressed in a host cell, and in a more specific manner relates to a method for manufacturing a protein that results in reduced levels of product-related impurities.

Abstract: A method, apparatus, and computer program product are therefore provided for providing a navigation user interface. The apparatus may be caused to: receive an indication of an origin and a destination; provide for presentation of a representation of the origin, a representation of the destination, and a representation of the route there between, where the representation of the route may include a bar extending in a circular shape between the representation of the origin and the representation of the destination, and defining a map display region within the circular shape. The apparatus may also be configured to provide for presentation of a present location indicator on the representation of the route and provide for presentation of a map within the map display region. The map within the map display region may correspond to at least one of a current location or a user selected location along the route.

Abstract: A method, apparatus and computer program product are provided for providing a destination preview while using a navigation device. As a user approaches a destination, a mode of navigation assistance may change from route guidance to destination preview. The destination preview may include an overhead perspective of an area surrounding a destination. The destination preview may be animated so as to allow the user to maintain perspective of the current location, planned route, and other objects while previewing the destination. The animated perspective path, including height, zoom level, angle, and speed of a vantage point, may be calculated so as to provide improved visibility for a user.

Abstract: A method, apparatus, and computer program product are therefore provided for providing a navigation user interface. The apparatus may be caused to: receive an indication of an origin and a destination; provide for presentation of a representation of the origin, a representation of the destination, and a representation of the route there between, where the representation of the route may include a bar extending in a circular shape between the representation of the origin and the representation of the destination, and defining a map display region within the circular shape. The apparatus may also be configured to provide for presentation of a present location indicator on the representation of the route and provide for presentation of a map within the map display region. The map within the map display region may correspond to at least one of a current location or a user selected location along the route.

Abstract: A method, apparatus and computer program product are provided for providing a destination preview while using a navigation device. As a user approaches a destination, a mode of navigation assistance may change from route guidance to destination preview. The destination preview may include an overhead perspective of an area surrounding a destination. The destination preview may be animated so as to allow the user to maintain perspective of the current location, planned route, and other objects while previewing the destination. The animated perspective path, including height, zoom level, angle, and speed of a vantage point, may be calculated so as to provide improved visibility for a user.

Abstract: A processor includes a first circuit and a second circuit. The first circuit is configured to provide a first indication of whether or not at least one reservation is valid in the processor. A reservation is established responsive to processing a load-linked instruction, which is a load instruction that is architecturally defined to establish the reservation. A valid reservation is indicative that one or more bytes indicated by the target address of the load-linked instruction have not been updated since the reservation was established. The second circuit is coupled to receive the first indication. Responsive to the first indication indicating no valid reservation, the first circuit is configured to select a speculative load-linked instruction for issued. The second circuit is configured not to select the speculative load-linked instruction for issue responsive to the first indication indicating the at least one valid reservation. A method is also contemplated.