Patents by Inventor Mark Perisich

Mark Perisich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and devices for providing an interrupt scheme in automated pharmaceutical dispensing machines without centralized arbitration
    Patent number: 7668998
    Abstract: In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 23, 2010
    Assignee: Parata Systems, LLC
    Inventors: Mark Perisich, Mark Alan Uebel
  • METHODS, SYSTEMS, AND DEVICES FOR PROVIDING AN INTERRUPT SCHEME IN AUTOMATED PHARMACEUTICAL DISPENSING MACHINES WITHOUT CENTRALIZED ARBITRATION
    Publication number: 20090177827
    Abstract: In a method for communication between a master node and a plurality of slave nodes connected by a bus therebetween, a first interrupt request is asserted by one of the plurality of slave nodes via a primary interrupt line. The plurality of slave nodes are electrically connected by the primary interrupt line. A unique delay time for requesting an interrupt is associated with each of the plurality of slave nodes. A second interrupt request is asserted by the one of the plurality of slave nodes via a secondary interrupt line electrically connecting the plurality of slave nodes. The second interrupt request is asserted in response to successfully asserting the first interrupt request and after the unique delay time associated with the one of the plurality of slave nodes. A message is then transmitted from the one of the plurality of slave nodes to the master node via the bus.
    Type: Application
    Filed: August 5, 2008
    Publication date: July 9, 2009
    Inventors: Mark Perisich, Mark Alan Uebel