Abstract: A load lock of a semiconductor processing tool includes a plurality of antechambers selectively isolatable from the main chamber of the load lock. The antechambers can function in tandem, serving as staging areas to enable maximum efficiency of wafer handling as the tool transfers wafers between various processing stages. The antechambers can also operate independently, with one antechamber isolated from the evacuated main load lock chamber and then vented, thereby permitting loading or unloading of cassettes or wafers while the main load lock chamber, the tool, and other antechambers remain occupied with wafer processing. In addition to wafer evacuation/venting, load lock antechambers in accordance with embodiments of the present invention may host a variety of other pre- or post-processing activities, such as wafer heating/cooling, exposure to purge/ambient gases, wafer orientation, wafer center-finding, and metrology.

Abstract: A method and apparatus for analyzing schedules for multi-cluster tools that are used in semiconductor wafer processing and similar manufacturing applications. The method and apparatus comprise a schedule analyzer and a pass-through chamber manager. The apparatus allows the user to analyze N! possible scheduling routines (algorithms) for a given multi-cluster tool configuration and a given N-step process sequence. The invention derives a plurality of possible scheduling algorithms for a given set of input parameters and then compares the algorithms by allowing either the user or an automated process to assign each processing step within the proposed schedule a rank ordered priority. Other process or wafer movement parameters may also be given ranges such that the invention can automatically derive optimal schedules with respect to various parameter values.