Abstract: An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having contents pointing to an instruction to be processed in said memory; an instruction register for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit for calculating addresses; an incrementing stage for incrementing the contents of said address register; and a multiplexer for selecting a calculated address or an incremented successor address. One embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit. Another embodiment also includes a first additional memory unit; a second additional memory unit; an address comparator; and a third additional memory unit.

Abstract: A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.

Abstract: A software programmable logic array ("SPLA") is disclosed for creating a logic array which can be dynamically programmed to provide any combination of predetermined outputs from any combination of desired inputs. The foregoing is accomplished by providing a first plane of programmable bits for producing a plurality of AND terms which are input to a second plane of programmable bits for producing a plurality of OR terms, which are then input into a third plane of programmable bits for producing a plurality of outputs, each having a desired polarity.

Abstract: A counter/timer circuit for a microcontroller includes a central register and two auxiliary registers each having transfer outputs and counting inputs. Bistable output storage elements are each connected to a respective one of the transfer outputs. Interrupt request flags are also each connected to a respective one of the transfer outputs. Start/stop elements are each connected to a respective one of the counting inputs. Input control blocks are each connected to a respective one of the start/stop elements. First reload, capture and compare units are connected between one of the auxiliary registers and the central register, and second reload, capture and compare units are connected between the other of the auxiliary registers and the central register.

Abstract: A circuit is disclosed which is implemented on the same silicon chip as a microprocessor to be utilized in a microprocessor system such as a microcontroller, which circuit allows a user to perform in-circuit emulation ("ICE") for the purpose of debugging the microprocessor system. The ICE circuitry comprises (i) capture logic which monitors the contents of the program address register and the internal data bus and various control lines of the processor; (ii) trace circuitry comprising a FIFO buffer which puts data from the capture logic to the output pins of the chip; and (iii) a content addressable memory and a software programmable logic array with emulation counters which together function as a finite state machine which performs the desired predetermined testing of the system.