Abstract: A multi-host endpoint reflector enables a method of communication between multiple USB hosts through the USB devices connected to them, where data from one USB host is routed across the USB devices between endpoints of complimentary directions to one or more additional USB hosts. The multi-host endpoint reflector may be integrated with a USB hub controller to form a USB compound device to create a multi-host endpoint reflector hub. A USB multi-host endpoint reflector hub enables a USB OTG B device to become a host upon request by providing a data bridge between the OTG B device after it has transitioned to a host role while any other OTG A device that already is a host is not required to change its host role to a slave role. Therefore a plurality of OTG host devices may co-exist on the same interconnection system hub and communicate there between.

Abstract: A multi-host endpoint reflector enables a method of communication between multiple USB hosts through the USB devices connected to them, where data from one USB host is routed across the USB devices between endpoints of complimentary directions to one or more additional USB hosts. The multi-host endpoint reflector may be integrated with a USB hub controller to form a USB compound device to create a multi-host endpoint reflector hub. A USB multi-host endpoint reflector hub enables a USB OTG B device to become a host upon request by providing a data bridge between the OTG B device after it has transitioned to a host role while any other OTG A device that already is a host is not required to change its host role to a slave role. Therefore a plurality of OTG host devices may co-exist on the same interconnection system hub and communicate there between.

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A simple clock source synchronous DDR data transfer mechanism may be combined with static bus state signaling to replace a complex bus (e.g. USB) with an easy to implement digital serial interconnect bus. This may eliminate various pull-up/pull-down resistors required in USB, and enable the interconnect bus to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The interconnect bus may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The digital serial interconnect bus may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract: A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.

Abstract: A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.

Abstract: A USB communications interface (USBCI) may enable communication between a high-speed USB device, e.g. a High-Speed-Inter-Chip (HSIC) USB device, and a non high-speed USB host, e.g. a full-speed USB host. The USBCI may receive first data from the USB host via a non high-speed transaction, and buffer the first data. The USBCI may also initiate a high-speed transaction corresponding to the non high-speed transaction to the USB device, and transmit at least a portion of the buffered first data to the USB device via the high-speed transaction. The USBCI may subsequently receive second data from the USB device via the high-speed transaction, and buffer the second data. The USBCI may also transmit at least a portion of the buffered second data to the USB host via the non high-speed transaction, and complete the non high-speed transaction upon the high-speed transaction completing.

Abstract: System and method for switching logic in a Universal Serial Bus hub. The USB hub may include upstream logic and downstream logic for sending and receiving information from a host controller and a USB device respectively. The USB hub may include a plurality of ports operable to couple to a plurality of devices, including a first port coupled to the upstream logic and a second port coupled to the downstream logic. The USB hub may also include switching logic operable to switch the upstream and the downstream logic with respect to the first port and the second port respectively. The switching logic may switch the upstream and downstream logic by decoupling the first port from the upstream logic, decoupling the second port from the downstream logic, and coupling the second port to the upstream logic. Additionally, the first port may be coupled to the downstream logic.

Abstract: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.

Abstract: System and method for enumerating and/or enumerating a device. The device may be a USB portable device which adheres to a first standard, e.g., the USB specification, and may engage in enumeration with respect to a USB hub/USB host device. Where a battery included in the device is sufficiently low, the device may engage in low power enumeration, e.g., to begin charging the device using enumerated power. Low power enumeration may allow the device to enumerate even when the device is incapable of powering on. Additionally, or alternatively, the device may determine whether the hub/host device is capable of providing high power charging. If it is, the device may begin charging the battery of the device using power provided by the hub/host device at a high power level.