Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first transceiver. The method further includes maintaining the first local oscillator at the first frequency and the second local oscillator at the second frequency during the transmitting of the first signal, during the receiving of the first signal, during the transmitting of the second signal, and during the receiving of the second signal.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.

Abstract: Wireless devices transmit and receive radio signals based upon reference frequencies generated by crystal oscillators. If the reference frequencies of the transmitter and the receiver are different, the radio signals may not be received properly or may not be received at all. A measurement circuit measures the amount of error or signal corruption in the radio signals due to the reference frequency offset between the transmitter and the receiver. A frequency offset circuit generates an offset operating frequency in the transmitter or the receiver to align or calibrate the operating frequencies of the devices.

Abstract: A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.

Abstract: A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.

Abstract: An improved Received Signal Strength Indicator (RSSI) circuit and method is provided herein for quickly and accurately detecting the strength of a received signal. The circuit described herein provides a more accurate RSSI signal, while consuming less power and die area, by utilizing digital rather than analog summing.

Abstract: Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

Abstract: A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

Abstract: A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.

Abstract: A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.

Abstract: Embodiments of a frequency modulated (FM) demodulator and associated methods are generally described. According to but one example embodiment, an apparatus is disclosed comprising a receiver front-end, to receive a signal from one or more antenna(e) and generate quadrature components of the received signal, and a frequency-shifted, cross-multiplied differentiator demodulator, coupled with the receiver front-end, to generate a demodulated representation of the received signal centered at a select intermediate frequency.

Abstract: A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.

Abstract: Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.

Abstract: An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.

Abstract: Embodiments of a frequency modulated (FM) demodulator and associated methods are generally described. According to but one example embodiment, an apparatus is disclosed comprising a receiver front-end, to receive a signal from one or more antenna(e) and generate quadrature components of the received signal, and a frequency-shifted, cross-multiplied differentiator demodulator, coupled with the receiver front-end, to generate a demodulated representation of the received signal centered at a select intermediate frequency.