Patents by Inventor Mark R. Hartoog
Mark R. Hartoog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5974245Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveability, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.Type: GrantFiled: May 30, 1997Date of Patent: October 26, 1999Assignee: VSLI Technology, Inc.Inventors: Ying-Meng Li, Sunil V. Ashtaputre, Jacob Greidinger, Mark R. Hartoog, Moazzem M. Hossain, Siu-Tong Hui
-
Patent number: 5856927Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process.Type: GrantFiled: May 1, 1995Date of Patent: January 5, 1999Assignee: VLSI Technology, Inc.Inventors: Jacob Greidinger, Mark R. Hartoog, Ara Markosian, Christine Fawcett, Eugenia Gelfund, Prasad Sakhamuri
-
Patent number: 5638291Abstract: The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.Type: GrantFiled: October 14, 1994Date of Patent: June 10, 1997Assignee: VLSI Technology, Inc.Inventors: Ying-Meng Li, Sunil V. Ashtaputre, Jacob Greidinger, Mark R. Hartoog, Moazzem M. Hossain, Siu-Tong Hui
-
Patent number: 5521836Abstract: A process for producing placement information for layouts of circuit elements of networks that are initially represented by netlists such that datapaths can be advantageously placed into a regular array. In one preferred embodiment, the method includes steps of encoding datapath information in instance names of a netlist generated by a datapath compiler; using the encoded datapath information for defining partitioned areas that preserve datapaths; and generating circuit layouts from the netlist, which layouts contain floor plans of the datapaths.Type: GrantFiled: December 12, 1994Date of Patent: May 28, 1996Assignee: VLSI Technology, Inc.Inventors: Mark R. Hartoog, James A. Rowson
-
Patent number: 5367469Abstract: A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.Type: GrantFiled: December 13, 1990Date of Patent: November 22, 1994Assignee: VLSI Technology, Inc.Inventor: Mark R. Hartoog
-
Patent number: 5313079Abstract: Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency.Type: GrantFiled: September 25, 1992Date of Patent: May 17, 1994Assignee: VLSI Technology, Inc.Inventors: Daniel R. Brasen, James D. Shiffer, II, Mark R. Hartoog, Sunil Asktaputre
-
Patent number: 5295088Abstract: A method estimates the interconnect capacitance of a first net in an integrated circuit. The first step of the method includes the generation of a value which indicates how tightly connected to one another are components connected to the first net. The second step of the method includes the prediction of interconnect capacitance of the first net based on the value generated in the first step and a number representing how many components are connected to the first net.Type: GrantFiled: July 9, 1993Date of Patent: March 15, 1994Assignee: VLSI Technology, Inc.Inventors: Mark R. Hartoog, Robert D. Shur
-
Patent number: 5197015Abstract: In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node.Type: GrantFiled: December 20, 1990Date of Patent: March 23, 1993Assignee: VLSI Technology, Inc.Inventors: Mark R. Hartoog, Thomas J. Schaefer, Robert D. Shur
-
Patent number: 5193092Abstract: An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.Type: GrantFiled: December 20, 1990Date of Patent: March 9, 1993Assignee: VLSI Technology, Inc.Inventors: Mark R. Hartoog, James A. Rowson, Robert D. Shur, Kenneth D. Van Egmond
-
Patent number: RE35671Abstract: A method for designing a circuit layout which includes the steps of supplying a predictive capacitance value for at least one net of a circuit layout, and placing and routing all nets of the circuit layout using at least one predictive capacitance value as a layout design constraint.Type: GrantFiled: July 17, 1996Date of Patent: November 25, 1997Assignee: VLSI Technology, Inc.Inventor: Mark R. Hartoog