Patents by Inventor Mark R. Kimmich

Mark R. Kimmich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508721
    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
  • Publication number: 20210233903
    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
  • Patent number: 10978448
    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson
  • Patent number: 10005662
    Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Alan Stringer, Mona Eissa, Byron J. R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
  • Publication number: 20170341934
    Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 30, 2017
    Inventors: Lee Alan Stringer, Mona Eissa, Byron J.R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
  • Patent number: 9771261
    Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: September 26, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Alan Stringer, Mona Eissa, Byron J. R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
  • Publication number: 20170267521
    Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Lee Alan Stringer, Mona Eissa, Byron J.R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
  • Publication number: 20170213956
    Abstract: An integrated circuit has a substrate, a circuit, a core structure, a first encapsulation layer, a second encapsulation layer, and an oxide layer. The circuit includes transistors with active regions developed on the substrate and a metal layer formed above the active regions to provide interconnections for the transistors. The core structure is formed above the metal layer. The first encapsulation layer covers the core structure, and it has a first thermal expansion coefficient. The second encapsulation layer covers the first encapsulation layer over the core structure, and it has a second thermal expansion coefficient that is different from the first thermal expansion coefficient. As a part of the stress relief structure, the oxide layer is formed above the second encapsulation layer. The oxide layer includes an oxide thickness sufficient to mitigate a thermal stress between the first and second encapsulation layers.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Mona M. Eissa, Mark R. Kimmich, Sudtida Lavangkul, Sopa Chevacharoenkul, Mark L. Jenson