Patents by Inventor Mark R. Nethercot

Mark R. Nethercot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and implementation of cyclic redundancy check for wide databus
    Patent number: 8539326
    Abstract: A method for computing a X-bit cyclical redundancy check (CRC-X) frame value for a data frame transmitted over a N-bit databus is provided. The method includes receiving a N-bit data input with an end-of-frame for the data frame at bit position M on the N-bit databus, performing a bitwise XOR on X most significant bits of the N-bit data input with a CRC-X feedback value to form a first N-bit intermediate data. The method also includes shifting the first N-bit intermediate data by M bit positions to align the end-of-frame of the data frame with a least significant bit (LSB), and padding M number of zero bits to a most significant bit (MSB) of the first N-bit intermediate data to form a second N-bit intermediate data.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 17, 2013
    Assignee: Xilinx, Inc.
    Inventors: Mark R. Nethercot, Martin B. Rhodes, Gareth D. Edwards
  • Method and apparatus for controlling an operating mode for an embedded Ethernet media access controller
    Patent number: 8284801
    Abstract: Method and apparatus for controlling an operating mode of an Ethernet media access controller (MAC) embedded in a programmable device is described. In some examples, a configuration circuit is configured to receive a configuration signal from configuration memory of the programmable device and a host signal from a host bus of the programmable device, and configured to output a control length check disable signal the value of which depends on the value of at least one of the configuration signal or the host signal. A parameter check circuit is configured to receive a control signal derived from at least one of the control length check disable signal or the configuration signal, and configured to selectively disable checking a length of each control frame in frames received by the Ethernet MAC based on a value of the control signal.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 9, 2012
    Assignee: Xilinx, Inc.
    Inventors: Mehulkumar R. Vashi, Robert Yin, Jayant Mittal, Nicholas McKay, Julian Kain, Martin B. Rhodes, Mark R. Nethercot
  • Automatic input/output timing adjustment flow for programmable integrated circuits
    Patent number: 8201123
    Abstract: A method of tuning an input/output (I/O) interface of a circuit design for a selected programmable integrated circuit can include determining whether the I/O interface meets a timing requirement and when the I/O interface does not meet the timing requirement, automatically adjusting a first timing setting of the I/O interface of the circuit design. The method can include iteratively determining whether the I/O interface meets the timing requirement, and responsive to each iteration, adjusting the first timing setting. The circuit design, including the adjusted first timing setting, can be output.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Xilinx, Inc.
    Inventors: Mark R. Nethercot, Stuart A. Nisbet