Abstract: An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.

Abstract: An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability.

Abstract: A circuit for detecting multiple address matches in an associative array includes a match current generator that responds to active match signals generated by the associative array by generating a match current that is linearly proportional to the number of active match signals generated by the array. A reference current source generates a reference current that is between one and two times greater than the match current when a single active match signal is generated by the associative array. A comparator compares the match current and the reference current and generates an active output signal when the match current is greater than the reference current.

Abstract: A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

Abstract: A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.