Abstract: A memory device includes at least three digital storage circuits arranged in parallel, the digital storage circuits each configured to store state data representing a bit of data in a first or second state; a data input configured to receive input data, the input data representing a bit of data in the first or second state; a voter having a voter output, the voter configured to generate output data at the voter output, the output data representing which of the first and second state are in a majority among the state data stored in each of the digital storage circuits; and a multiplexer operatively coupled to the data input, the voter output, and an input of each of the digital storage circuits, the multiplexer configured to output, to each of the digital storage circuits, one of the input data and the output data based on a functional enable signal.

Abstract: Techniques are provided for an error resistant radiation hardened memory system based on spreading of data bits among multiple random access memories (RAMs). A memory system implementing the techniques according to an embodiment includes a first plurality of RAMs configured to store data bits written to the memory system, the data bits distributed over the first plurality of RAMs. The system also includes an error correction coding (ECC) circuit configured to generate ECC codes, each of the codes associated with a unique group of the data bits. The system further includes a second plurality of RAMs configured to store bits of the ECC codes such that the bits of each ECC code are distributed over the second plurality of RAMs. The system further includes a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory system.

Abstract: A memory device includes at least three digital storage circuits arranged in parallel, the digital storage circuits each configured to store state data representing a bit of data in a first or second state; a data input configured to receive input data, the input data representing a bit of data in the first or second state; a voter having a voter output, the voter configured to generate output data at the voter output, the output data representing which of the first and second state are in a majority among the state data stored in each of the digital storage circuits; and a multiplexer operatively coupled to the data input, the voter output, and an input of each of the digital storage circuits, the multiplexer configured to output, to each of the digital storage circuits, one of the input data and the output data based on a functional enable signal.

Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.

Abstract: A method and apparatus for forming laminate composite structures. At least two laminae, each containing electrically conductive reinforcing fibers, are placed upon each other in contacting relationship to form a generally layered structure. The layered structure may be subjected to heat to conductively transfer heat through the layered structure and thereby improve the surface contact between the two laminae. The layered structure is volumetrically heated by inductively transferring energy to the electrically conductive reinforcing fibers. The heated, layered structure is consolidated, such as by applying pressure and reducing the temperature of the layered structure. The consolidated structure is then quenched by rapidly cooling the consolidated structure in a directionally controlled manner about a midplane thereof.

Abstract: A method and apparatus for forming laminate composite structures. At least two laminae, each containing electrically conductive reinforcing fibers, are placed upon each other in contacting relationship to form a generally layered structure. The layered structure may be subjected to heat to conductively transfer heat through the layered structure and thereby improve the surface contact between two laminae. The layered structure is volumetrically heated by inductively transferring energy to the electrically conductive reinforcing fibers. The heated, layered structure is consolidated, such as by applying pressure and reducing the temperature of the layered structure. The consolidated structure is then quenched by rapidly cooling the consolidated structure in a directionally controlled manner about a midplane thereof.

Abstract: A method and apparatus for forming laminate composite structures. At least two laminae, each containing electrically conductive reinforcing fibers, are placed upon each other in contacting relationship to form a generally layered structure. The layered structure may be subjected to heat to conductively transfer heat through the layered structure and thereby improve the surface contact between the two laminae. The layered structure is volumetrically heated by inductively transferring energy to the electrically conductive reinforcing fibers. The heated, layered structure is consolidated, such as by applying pressure and reducing the temperature of the layered structure. The consolidated structure is then quenched by rapidly cooling the consolidated structure in a directionally controlled manner about a midplane thereof.