Abstract: A dual-voltage receiver, comprising a voltage detector. A high voltage Schmitt trigger coupled to the voltage detector. A low voltage Schmitt trigger coupled to the voltage detector. A combined level shifter coupled to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is on and the low voltage Schmitt trigger is off when the voltage detector outputs a high voltage detect signal.

Abstract: A dual-voltage receiver, comprising a voltage detector. A high voltage Schmitt trigger coupled to the voltage detector. A low voltage Schmitt trigger coupled to the voltage detector. A combined level shifter coupled to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is on and the low voltage Schmitt trigger is off when the voltage detector outputs a high voltage detect signal.

Abstract: Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged.

Abstract: The present invention significantly reduces the chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for output impedance drivers, such as, but not limited to, double data rate (DDR2) synchronous dynamic random access memory (SDRAM). In an embodiment of the invention, a voltage drop across the driver is a decreased ratio of the supply voltage, e.g., three-tenths of the supply voltage, lower than half of the supply voltage. A smaller voltage drop allows a lower current and a higher impedance to be used in the driver. By having a higher impedance across the driver, the physical area needed for the DDR2 driver is reduced because a transistor with a smaller physical width can be used. A DDR2 driver operating at the decreased ratio is the functional equivalent of the driver operating with the supply voltage or half of the supply voltage, with the added advantage of the reduced area.

Abstract: Disclosed herein are embodiments of electrostatic discharge (ESD) protection circuits. In certain embodiments an ESD protection circuit may include two series resistor-capacitor (RC) circuits. One series RC circuit may have a short time constant and may selectively activate a current shunt between two power rails in response to an ESD event. Accordingly, the ESD circuit may be able to respond to fast ramping ESD events. The other series RC circuit has a longer time constant, and maintains the current shunt in an active state for a sufficient amount of time to allow the ESD event to be completely discharged.

Abstract: An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

Abstract: An integrated circuit comprising a relatively simple high voltage tolerant output circuit that may be placed in a high impedance state (i.e., tri-stated) when the voltage at a corresponding signal connection point reaches a predetermined voltage reflecting a logic high level. In one embodiment of the invention, the output circuit is responsive to assertion of a control signal to selectively enter a high impedance state. The control signal is asserted by a control circuit following the detection of a logic high signal of a predetermined duration at the external signal connection point. The predetermined duration may correspond to transmission line delays of a signal line driven by the output circuit. For example, the delay in placing the output circuit in a high impedance state may correspond to the length of time needed to allow transmission line reflections to dissipate to an acceptable level.

Abstract: A single clamp circuit for integrated circuits with multiple V.sub.dd power pins by coupling the various V.sub.dd busses to an ESD clamped V.sub.dd bus or pseudo- V.sub.dd bus via diodes. The diodes will provide coupling from any V.sub.dd bus to the clamp circuit during a positive ESD transient. A diode for each V.sub.dd bus and a single clamp circuit can be much more area efficient than a single clamp circuit for each V.sub.dd bus. During normal operation, the diodes will become weakly forward biased due to the leakage current of the clamp circuit. Small signal noise will tend not to be coupled from one bus to the other because of the high impedance of the diodes. For a large positive noise transient on one bus, the other bus diode will reverse bias, thus decoupling the signal from the other busses. A large negative noise transient on one bus will cause its diode to reverse bias thus decoupling it from the other busses.

Abstract: A MOS time delay circuit including a MOS regulated voltage supply circuit for supplying a voltage proportional to a predetermined trigger voltage and a RC delay circuit having a first input connected to the regulated voltage supply circuit, and a second input connected to the signal input, and an output. The circuit also includes a variable trigger point inverter having an input connected to the output of the RC delay circuit, and signal output.

Abstract: A static read only memory fabricated with field effect transistors of either the depletion type or the enhancement type connected in series. The read only memory includes a compact sensing circuit for detecting relatively small voltage swings at each node corresponding to a bit line of the memory cell, and a highly sensitive differential sense amplifier including first and second cascaded connected inverter stages.