Abstract: A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.

Abstract: A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.

Abstract: A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

Abstract: A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.