Abstract: An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form, a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Abstract: A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is preferably made from polysilicon or silicon. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then removed, preferably using a plasma etch process.

Abstract: A single interpoly dielectric layer is provided for use in semiconductor devices. The single interpoly dielectric layer being formed of silicon graded such that certain regions within the single interpoly dielectric layer are either oxygen-rich or nitrogen-rich. The single interpoly dielectric layer can be formed in-situ within a single deposition tool. In certain embodiments, the resulting single interpoly dielectric layer can be made thinner and/or can be formed to provide improved dielectric characteristics when compared to a conventional oxide-nitride-oxide (ONO) interpoly dielectric layer that has three separate and unique layers. Thus, the single interpoly dielectric layer is highly desirable for use in reduced-size semiconductor devices and/or semiconductor devices requiring improved data retention capabilities, such as non-volatile memory cells.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted after the ONO layer and junction areas have been formed. The entire semiconductor structure is heated to anneal out the nitrogen implant damage and to diffuse or drive the implanted nitrogen into the substrate and silicon oxide interface to form strong SiN bonds at that interface. By implanting nitrogen into the ONO stack, instead of a single silicon oxide layer as done conventionally, damage to the underlying silicon substrate is reduced. This results in better isolation between adjacent bit lines and suppresses leakages between adjacent bit lines.

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract: Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: A method for forming viable floating gate memory cells in a semiconductor substrate. At various points within the memory cell manufacturing process rapid thermal annealing is used to repair any damage that may be caused to the crystals in the substrate by various processing steps. By quickly repairing any damage to the crystals of the substrate, the rate and amount of overall transient enhanced diffusion of the various dopants within the substrate can be greatly reduced, thereby allowing the production of a viable memory cell. Specifically, the present invention uses rapid thermal annealing during and following the formation of the source and drain regions and the interconnection regions effecting electrical connection between the source regions. This desensitizes the erase rates of the semiconductor device to the etching conditions employed to form the connections.

Abstract: Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

Abstract: A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

Abstract: Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Abstract: Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.