Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

Abstract: A process for replacing a first soft-top of a convertible-top of a motor vehicle with a second soft-top includes removing the first soft-top from the convertible-top. The first soft-top is separated from a headliner of the convertible-top. The second soft-top is selected. The second soft-top has a window larger than a window of the first soft-top. A plurality of receptacles are fixed to an edge of the larger window. The second soft-top is attached to the motor vehicle. The larger window is connected directly to the headliner by engaging headliner anchors with the receptacles fixed to the larger window.

Abstract: A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.

Abstract: A voice browser dialog enabler for multimodal dialog uses a multimodal markup document with fields have markup-based forms associated with each field and defining fragments. A voice browser driver resides on a communication device and provides the fragments and identifiers that identify the fragments. A voice browser implementation resides on a remote voice server and receives the fragments from the driver and downloads a plurality of speech grammars. Input speech is matched against those speech grammars associated with the corresponding identifiers received in a recognition request from the voice browser driver.

Abstract: An iron fortification complex which may be used to fortify foods and beverages with iron. The complex is formed of ferric ions and caseinate. The complex is sufficiently stable as to be suitable for use in retorted products. However, despite the stability, the iron in the complexes has substantially the same bioavailability as ferrous sulfate.

Abstract: A dictionary is comprised of a dendroid hierarchy of branches and nodes, wherein each node represents no more than one symbol (which symbol is to be converted to a corresponding sound) and wherein each such symbol as is represented at a given node has only one corresponding sound associated with that symbol at that node. In addition, many of the branches include a plurality of nodes representing a string of the symbols in a particular sequence. The dictionary is used to translate an input comprising a given integral sequence of the symbols into a corresponding integral sequence of sounds. This permits both method and apparatus to convert, for example, text to representative phonemes. Such phonemes can be used, amongst other purposes, to support synthesized speech production.

Abstract: An iron-protein hydrolysate complex which may be used to fortify foods and beverages with iron. The complex is formed of ferrous ions chelated to partially hydrolyzed egg white protein. The hydrolyzed egg white protein has a molecular weight in the range of about 500 to about 10,000. The complexes are sufficiently stable as to be suitable for use in sterilized products, such as retorted products. Moreover, despite the stability, the iron in the complexes has substantially the same bioavailability as ferrous sulfate.

Abstract: A replaceable roller bogie for a single sheet feeder includes pre-feed and separation rollers mounted on a frame which also has a frame positioning lever thereon. Roller drive gears are mounted between spaced plates on the frame and include a pre-feed roller clutch gear with elastomeric teeth which is mounted in slots on the frame which limit motion travel of the clutch gear to prevent over engagement of gear teeth on the clutch gear with gear teeth on the pre-feed roller drive gear. The replaceable bogie is pivotally supported on the sheet feeder and held in place by a manually operable release and latch mechanism.

Abstract: Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.

Abstract: A process for replacing a first soft-top of a convertible-top of a motor vehicle with a second soft-top includes separating the first soft-top from a headliner of the convertible-top and removing the first soft-top from the convertible top. The second soft-top is selected. The second soft-top has a window at least as large as a window of the first soft-top. A plurality of receptacles are fixed to the second soft-top. The second soft-top is attached to the motor vehicle. The second soft-top is connected directly to the headliner by engaging headliner anchors with the receptacles fixed to the second soft-top.

Abstract: Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

Abstract: One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

Abstract: A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

Abstract: A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.

Abstract: A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

Abstract: A replaceable roller bogie for a single sheet feeder includes pre-feed and separation rollers mounted on a frame which also has a frame positioning lever thereon. Roller drive gears are mounted between spaced plates on the frame and include a pre-feed roller clutch gear with elastomeric teeth which is mounted in slots on the frame which limit motion travel of the clutch gear to prevent over engagement of gear teeth on the clutch gear with gear teeth on the pre-feed roller drive gear. The replaceable bogie is pivotally supported on the sheet feeder and held in place by a manually operable release and latch mechanism.

Abstract: Photochemical tissue boding methods for bonding neural tissues include the application of a photosensitizer to a tissue and/or tissue graft, followed by irradiation with electromagnetic energy to produce a tissue seal. The methods are useful for tissue adhesion, such as in wound closure, tissue grafting, skin grafting, musculoskeletal tissue repair, ligament or tendon repair, neural repair, blood vessel repair and corneal repair.

Abstract: A sheet transfer apparatus includes a first roller, a second roller and a power train. The first roller is configured to be rotatably driven at a first surface speed. The second roller is spaced from the first roller such that the first roller and the second roller are configured to simultaneously engage a media sheet. The second roller is configured to be driven at a second surface speed greater than the first surface speed. The power train delivers power to the first roller to rotatably drive the first roller. The power train includes a first gear coupled to the first roller, a second gear and a third gear. The third gear is movable between a first position in which the third gear is in power transmitting engagement with both the first gear and the second gear and a second position in which the third gear is out of power transmitting engagement with the second gear.

Abstract: An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.