Patents by Inventor Mark Raymond

Mark Raymond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961036
    Abstract: Systems and methods provide real-time shipping optimization recommendations for reducing the cost of shipping freight units in a shipment. System comprises a measurement system in communication with a computer system that comprises a client computer device in communication with a host computer system. The measurement system comprises multiple sensing devices to determine weight, dimensions, and other shipping parameters of the freight units in the shipment. The computer system computes a current shipping cost and density based on the shipping parameters. The computer system determines shipping recommendations including recommended adjustments to the shipping parameters that reduce the current shipping cost. The shipping recommendations are transmitted to the client computer device prior to loading the shipment onto a carrier vehicle for the shipment.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 16, 2024
    Assignee: FIDA, LLC
    Inventors: Michael Wagner, Mark Raymond, Terrance J. Henderson, II, Christine Henderson
  • Publication number: 20220318748
    Abstract: Systems and methods provide real-time shipping optimization recommendations for reducing the cost of shipping freight units in a shipment. System comprises a measurement system in communication with a computer system that comprises a client computer device in communication with a host computer system. The measurement system comprises multiple sensing devices to determine weight, dimensions, and other shipping parameters of the freight units in the shipment. The computer system computes a current shipping cost and density based on the shipping parameters. The computer system determines shipping recommendations including recommended adjustments to the shipping parameters that reduce the current shipping cost. The shipping recommendations are transmitted to the client computer device prior to loading the shipment onto a carrier vehicle for the shipment.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Michael Wagner, Mark Raymond, Terrance J. Henderson, II, Christine Henderson
  • Patent number: 11379788
    Abstract: Systems and methods provide real-time shipping optimization recommendations for reducing the cost of shipping freight units in a shipment. System comprises a measurement system in communication with a computer system that comprises a client computer device in communication with a host computer system. The measurement system comprises multiple sensing devices to determine weight, dimensions, and other shipping parameters of the freight units in the shipment. The computer system computes a current shipping cost and density based on the shipping parameters. The computer system determines shipping recommendations including recommended adjustments to the shipping parameters that reduce the current shipping cost. The shipping recommendations are transmitted to the client computer device prior to loading the shipment onto a carrier vehicle for the shipment.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: July 5, 2022
    Assignee: FIDA, LLC
    Inventors: Michael Wagner, Mark Raymond, Terrance J. Henderson, II, Christine Henderson
  • Patent number: 11031484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 8, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: George R. Mulfinger, Judson R. Holt, Mark Raymond
  • Publication number: 20200411666
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: George R. MULFINGER, Judson R. HOLT, Mark RAYMOND
  • Patent number: 10854515
    Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 1, 2020
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Vimal Kamineni, Ruilong Xie, Mark Raymond
  • Publication number: 20200168504
    Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Ruilong Xie, Mark Raymond
  • Patent number: 10643894
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 5, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Patent number: 10593593
    Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Ruilong Xie, Mark Raymond
  • Publication number: 20200035556
    Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Ruilong Xie, Mark Raymond
  • Patent number: 10283608
    Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank Mont, Mark Raymond, Chengyu Niu
  • Publication number: 20180269297
    Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 20, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan ZHANG, Frank MONT, Mark RAYMOND, Chengyu NIU
  • Publication number: 20180116316
    Abstract: A clothing pocket insert includes: an anchoring portion defining a longitudinal axis and configured to reside within a pocket of a torso garment; an arm extending from the anchoring portion transversely relative to the longitudinal axis; and a connecting portion connected to the arm and configured to couple with an electrical device.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 3, 2018
    Inventor: Mark Raymond
  • Publication number: 20180006141
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Application
    Filed: May 17, 2017
    Publication date: January 4, 2018
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Publication number: 20180006140
    Abstract: Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of the trench is recessed. A trench contact epitaxial layer is formed in the trench. An oxide layer is formed on top of the trench contact epitaxial layer in the trench. A metal oxide layer is formed on top of the oxide layer in the trench. A metal contact is formed on top of the metal oxide layer, where the oxide layer and the metal oxide layer together form a dipole layer.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Jody Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark Raymond, Tenko Yamashita
  • Publication number: 20150349069
    Abstract: A FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. A first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer is positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. A metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventors: Ruilong Xie, Mark Raymond, Robert Miller
  • Patent number: 9147765
    Abstract: Disclosed herein are various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices. One illustrative device disclosed herein includes a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches at least partially define a fin for the device, an etch stop layer positioned above a bottom surface of each of the trenches, and a metal silicide region formed on all exposed surfaces of the fin that are positioned above an upper surface of the etch stop layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Mark Raymond, Robert Miller
  • Patent number: 8652963
    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: February 18, 2014
    Assignees: GLOBALFOUNDRIES, Inc., International Business Machines Corporation
    Inventors: Bin Yang, Christian Lavoie, Emre Alptekin, Ahmet S. Ozcan, Cung D. Tran, Mark Raymond
  • Publication number: 20130187228
    Abstract: Disclosed herein are various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices. One illustrative device disclosed herein includes a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches at least partially define a fin for the device, an etch stop layer positioned above a bottom surface of each of the trenches, and a metal silicide region formed on all exposed surfaces of the fin that are positioned above an upper surface of the etch stop layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Mark Raymond, Robert Miller
  • Publication number: 20130069124
    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Bin Yang, Christian Lavoie, Emre Alptekin, Ahmet S. Ozcan, Cung D. Tran, Mark Raymond