Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Abstract: A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

Abstract: In one example, a circuit for comparing current drawn by a selected memory cell for a vector-matrix-multiplier with current drawn by a reference matrix comprises a first circuit comprising a first PMOS transistor coupled to a first NMOS transistor coupled to the selected memory cell; and a second circuit comprising a second PMOS transistor coupled to a second NMOS transistor coupled to the reference matrix; wherein a node between the second PMOS transistor and the second NMOS transistor outputs a current indicative of a value stored in the selected memory cell.

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Abstract: Numerous output circuits are disclosed for an analog neural memory system for a deep learning neural network. In one embodiment, an adaptable neuron circuit receives output current from a neuron and converts it into a voltage. In another embodiment, a current sample and hold circuit samples an input current and generates an output current. In another embodiment, a voltage sample and hold circuit samples an input voltage and generates an output voltage.

Abstract: Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.

Abstract: Numerous embodiments of programming, verifying, and reading systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells can be programmed and verified with extreme precision to hold one of N different values. During a read operation, the system determines which of the N different values is stored in a selected cell.

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

Abstract: Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one example, a circuit comprises a digital-to-analog converter to convert a target weight comprising digital bits into a target voltage, a current-to-voltage converter to convert an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator to compare the output voltage to the target voltage during a verify operation.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.