Patents by Inventor Mark Ren

Mark Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164570
    Abstract: A group head (20) for an espresso machine (10), the group head (20) comprising: a group head bracket (36) for detachable engagement with a portafilter (30) holding a puck (22) of ground coffee in a filter basket (64) to dispense an espresso coffee; a conduit (34) for receiving a flow of water to the portafilter (30); and, a heater (32) mounted in the group head (20) to heat the flow of water to the portafilter (30).
    Type: Application
    Filed: March 24, 2022
    Publication date: May 23, 2024
    Applicant: Breville Pty Limited
    Inventors: Mark Lewis HOLLOWAY, Alper BENDER, Man Ho HAN, Chiu Keung Kenneth LEE, Con PSAROLOGOS, Xiang REN, Alexander Lee Thomas CHUDLEY
  • Patent number: 10489542
    Abstract: A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 26, 2019
    Assignee: NVIDIA Corp.
    Inventors: Mark Ren, Brucek Khailany
  • Publication number: 20190325092
    Abstract: A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Mark Ren, Brucek Khailany