Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Systems, methods and computer program products assess processor performance metrics by monitoring probes constructed using instruction sequences. A first probe value can be determined from execution of a broad spectrum probe in an execution environment. In response to determining that the first probe value is not a first expected probe value, a targeted probe providing a second probe value directed to a subsystem of the execution environment, a feature of the subsystem, or a component of the execution environment is executed. In response to determining that the second probe value is not a second expected probe value, a differential between the second probe value and the second expected probe value can be used to determine that a bottleneck exists in at least one of the subsystem of the execution environment, the feature of the subsystem, or the component of the execution environment.

Abstract: Processor performance metrics are assessed by monitoring probes constructed using instruction sequences. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Monitoring probes constructed using instruction sequences are used to assess processor performance metrics. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Processor performance metrics are assessed by monitoring probes constructed using instruction sequences. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second. probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Monitoring probes constructed using instruction sequences are used to assess processor performance metrics. A probe comprising an instruction sequence is selected. The instruction sequence can be configured to measure at least one hardware metric. A first probe value is received. The first probe value can be based, at least in part, on the hardware metric. The first probe value can be determined from execution of the probe in a first execution environment. The probe can be executed a second time to determine a second probe value. The second probe value can be based, at least in part, on the hardware metric. The second probe value is determined in a second execution environment including at least one workload. The first probe value and the second probe value can be compared to produce a performance assessment of the second execution environment.

Abstract: Disclosed is an apparatus, method, and program product for identifying and grouping threads that have interdependent data access needs. The preferred embodiment of the present invention utilizes two different constructs to accomplish this grouping. A Memory Affinity Group (MAG) is disclosed. The MAG construct enables multiple threads to be associated with the same node without any foreknowledge of which threads will be involved in the association, and without any control over the particular node with which they are associated. A Logical Node construct is also disclosed. The Logical Node construct enables multiple threads to be associated with the same specified node without any foreknowledge of which threads will be involved in the association. While logical nodes do not explicitly identify the underlying physical nodes comprising the system, they provide a means of associating particular threads with the same node and other threads with other node(s).

Abstract: Multiple database queries are satisfied with the same data in a manner that assures the data is current and without having to interrogate the database for each query. In a first embodiment, all queries that are received during the processing of a first query after interrogation of the database has begun for the first query are evaluated to determine whether the result set returned for the first query will satisfy the queries received during processing of the first query. If so, the result set returned for the first query is used to generate result sets for the subsequent compatible queries received during the processing of the first query. In a second embodiment, queries are delayed and grouped, and a new query is then processed for each group that returns a result set that satisfies all of the queries in the group. In both cases, the result set for one query is used to generate a result set for a different query.

Abstract: Disclosed is an apparatus, method, and program product for identifying and grouping threads that have interdependent data access needs. The preferred embodiment of the present invention utilizes two different constructs to accomplish this grouping. A Memory Affinity Group (MAG) is disclosed. The MAG construct enables multiple threads to be associated with the same node without any foreknowledge of which threads will be involved in the association, and without any control over the particular node with which they are associated. A Logical Node construct is also disclosed. The Logical Node construct enables multiple threads to be associated with the same specified node without any foreknowledge of which threads will be involved in the association. While logical nodes do not explicitly identify the underlying physical nodes comprising the system, they provide a means of associating particular threads with the same node and other threads with other node(s).

Abstract: Disclosed is an apparatus, method, and program product for identifying and grouping threads that have interdependent data access needs. The preferred embodiment of the present invention utilizes two different constructs to accomplish this grouping. A Memory Affinity Group (MAG) is disclosed. The MAG construct enables multiple threads to be associated with the same node without any foreknowledge of which threads will be involved in the association, and without any control over the particular node with which they are associated. A Logical Node construct is also disclosed. The Logical Node construct enables multiple threads to be associated with the same specified node without any foreknowledge of which threads will be involved in the association. While logical nodes do not explicitly identify the underlying physical nodes comprising the system, they provide a means of associating particular threads with the same node and other threads with other node(s).

Abstract: Multiple database queries are satisfied with the same data in a manner that assures the data is current and without having to interrogate the database for each query. In a first embodiment, all queries that are received during the processing of a first query after interrogation of the database has begun for the first query are evaluated to determine whether the result set returned for the first query will satisfy the queries received during processing of the first query. If so, the result set returned for the first query is used to generate result sets for the subsequent compatible queries received during the processing of the first query. In a second embodiment, queries are delayed and grouped, and a new query is then processed for each group that returns a result set that satisfies all of the queries in the group. In both cases, the result set for one query is used to generate a result set for a different query.

Abstract: A packet control mechanism for a computer data system that dynamically adjusts packet training depending on the utilization load on the processor. The dynamic adjustment of packet training can be to enable and disable packet training, or adjust the number of packets in the packet train. In preferred embodiments, the computer data system includes a processor utilization mechanism that indicates a load on a processor. When the packet control mechanism determines the load on the processor is above a threshold limit, the packet control mechanism reduces the processor load by compressing the packets into the packet train. The compressing of the packets is stopped or reduced when the processor load is below a threshold in order to increase the data throughput on the network interface.

Abstract: A packet control mechanism for a computer data system that dynamically adjusts packet training depending on the utilization load on the processor. The dynamic adjustment of packet training can be to enable and disable packet training, or adjust the number of packets in the packet train. In preferred embodiments, the computer data system includes a processor utilization mechanism that indicates a load on a processor. When the packet control mechanism determines the load on the processor is above a threshold limit, the packet control mechanism reduces the processor load by compressing the packets into the packet train. The compressing of the packets is stopped or reduced when the processor load is below a threshold in order to increase the data throughput on the network interface.

Abstract: A packet control mechanism for a computer data system that dynamically adjusts packet training depending on the utilization load on the processor. The dynamic adjustment of packet training can be to enable and disable packet training, or adjust the number of packets in the packet train. In preferred embodiments, the computer data system includes a processor utilization mechanism that indicates a load on a processor. When the packet control mechanism determines the load on the processor is above a threshold limit, the packet control mechanism reduces the processor load by compressing the packets into the packet train. The compressing of the packets is stopped or reduced when the processor load is below a threshold in order to increase the data throughput on the network interface.

Abstract: A packet control mechanism for a computer data system that dynamically adjusts packet training depending on the utilization load on the processor. The dynamic adjustment of packet training can be to enable and disable packet training, or adjust the number of packets in the packet train. In preferred embodiments, the computer data system includes a processor utilization mechanism that indicates a load on a processor. When the packet control mechanism determines the load on the processor is above a threshold limit, the packet control mechanism reduces the processor load by compressing the packets into the packet train. The compressing of the packets is stopped or reduced when the processor load is below a threshold in order to increase the data throughput on the network interface.

Abstract: Disclosed is an apparatus, method, and program product for observing the nodal workload balance of the system on an ongoing basis, and for dynamically changing the preferred nodes of existing threads in order to improve nodal balance. Workload balance is ascertained on a nodal basis and then thread-based workload information is collected. If the detected imbalance persists, the thread-based information is used to change the assignment of preferred nodes to threads to improve nodal workload balance.

Abstract: Disclosed is an apparatus, method, and program product for identifying and grouping threads that have interdependent data access needs. The preferred embodiment of the present invention utilizes two different constructs to accomplish this grouping. A Memory Affinity Group (MAG) is disclosed. The MAG construct enables multiple threads to be associated with the same node without any foreknowledge of which threads will be involved in the association, and without any control over the particular node with which they are associated. A Logical Node construct is also disclosed. The Logical Node construct enables multiple threads to be associated with the same specified node without any foreknowledge of which threads will be involved in the association. While logical nodes do not explicitly identify the underlying physical nodes comprising the system, they provide a means of associating particular threads with the same node and other threads with other node(s).

Abstract: Mechanism for Assigning Home Nodes to Newly Created Threads Disclosed is an apparatus, method, and program product for associating threads with the processing nodes of a multi-nodal computer system. The assignment is accomplished by considering both the relative work capacity of, and the relative amount of ongoing work assigned to, each node. Initiation Weights are used in the preferred embodiment to reflect the desired proportions of threads assigned to each node, from the standpoint of which node should be chosen when a new thread is created.