Patents by Inventor Mark Robert Visokay
Mark Robert Visokay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11710764Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.Type: GrantFiled: June 27, 2018Date of Patent: July 25, 2023Assignee: Texas Instruments IncorporatedInventors: Poornika Fernandes, Sagnik Dey, Luigi Colombo, Haowen Bu, Scott Robert Summerfelt, Mark Robert Visokay, John Paul Campbell
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Patent number: 11004929Abstract: Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.Type: GrantFiled: October 9, 2019Date of Patent: May 11, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dok Won Lee, Erika Lynn Mazotti, Mark Robert Visokay, William David French, Ricky Alan Jackson, Wai Lee
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Publication number: 20200119132Abstract: Various examples provide an electronic device that includes first and second resistor segments. Each of the resistor segments has a respective doped resistive region formed in a semiconductor substrate. The resistor segments are connected between first and second terminals. The first resistor segment is configured to conduct a current in a first direction, and the second resistor segment is configured to conduct the current in a second different direction. The directions may be orthogonal crystallographic directions of the semiconductor substrate.Type: ApplicationFiled: October 9, 2019Publication date: April 16, 2020Inventors: Dok Won Lee, Erika Lynn Mazotti, Mark Robert Visokay, William David French, Ricky Alan Jackson, Wai Lee
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Publication number: 20200006471Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Inventors: POORNIKA FERNANDES, SAGNIK DEY, LUIGI COLOMBO, HAOWEN BU, SCOTT ROBERT SUMMERFELT, MARK ROBERT VISOKAY, JOHN PAUL CAMPBELL
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Patent number: 10249621Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.Type: GrantFiled: December 15, 2016Date of Patent: April 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark Robert Visokay, Tae S. Kim, Mahalingam Nandakumar, Eric D. Rullan, Gregory B. Shinn
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Publication number: 20180175023Abstract: A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer is over the gate electrode. A contact masking material pattern is defined on the PMD layer including first contact defining features for forming active contacts and second contact defining features for forming dummy contacts (DC's) including over active areas and gate electrodes. Contacts are etched through the PMD layer using the contact masking material pattern to form active contacts and DC's. A patterned metal 1 (M1) layer is formed including first M1 portions over the active contacts and dummy M1 portions over the DC's. Metallization processing follows including forming interconnects so that the active contacts are connected to MOS transistors on the IC, and the DC's are not electrically connected to the MOS transistors.Type: ApplicationFiled: December 15, 2016Publication date: June 21, 2018Inventors: MARK ROBERT VISOKAY, TAE S. KIM, MAHALINGAM NANDAKUMAR, ERIC D. RULLAN, GREGORY B. SHINN
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Publication number: 20150221516Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.Type: ApplicationFiled: April 9, 2015Publication date: August 6, 2015Inventors: Mark Robert Visokay, Scott Robert Summerfelt
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Patent number: 8822236Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.Type: GrantFiled: July 24, 2013Date of Patent: September 2, 2014Assignee: Texas Instruments IncorporatedInventors: Bo-Yang Lin, Yen Lee, Haowen Bu, Mark Robert Visokay
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Publication number: 20140147940Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.Type: ApplicationFiled: November 25, 2013Publication date: May 29, 2014Applicant: Texas Instruments IncorporatedInventors: Mark Robert Visokay, Scott Robert Summerfelt
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Publication number: 20130309783Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Inventors: Bo-Yang Lin, Yen Lee, Haowen Bu, Mark Robert Visokay
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Publication number: 20130056811Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.Type: ApplicationFiled: March 28, 2012Publication date: March 7, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Bo-Yang Lin, Yen Lee, Haowen Bu, Mark Robert Visokay
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Patent number: 8273645Abstract: A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.Type: GrantFiled: August 7, 2009Date of Patent: September 25, 2012Assignee: Texas Instruments IncorporatedInventors: Mark Robert Visokay, Freidoon Mehrad, Richard L. Guldi, Yaw Samuel Obeng
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Publication number: 20110097884Abstract: A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.Type: ApplicationFiled: August 7, 2009Publication date: April 28, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mark Robert VISOKAY, Freidoon MEHRAD, Richard L. GULDI, Yaw Samuel OBENG
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Publication number: 20100323486Abstract: Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.Type: ApplicationFiled: January 29, 2010Publication date: December 23, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Joseph Chambers, Mark Robert Visokay
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Patent number: 7842567Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.Type: GrantFiled: November 14, 2008Date of Patent: November 30, 2010Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Luigi Colombo, Mark Robert Visokay
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Patent number: 7678675Abstract: Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.Type: GrantFiled: April 24, 2007Date of Patent: March 16, 2010Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Mark Robert Visokay
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Patent number: 7642146Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.Type: GrantFiled: January 5, 2007Date of Patent: January 5, 2010Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo
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Patent number: 7612422Abstract: Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.Type: GrantFiled: December 29, 2006Date of Patent: November 3, 2009Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Luigi Colombo, Mark Robert Visokay
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Patent number: 7601577Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.Type: GrantFiled: October 11, 2007Date of Patent: October 13, 2009Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo, Antonio Luis Pacheco Rotondaro
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Publication number: 20090068828Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.Type: ApplicationFiled: November 14, 2008Publication date: March 12, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Joseph Chambers, Luigi Colombo, Mark Robert Visokay