Patents by Inventor Mark Rollins
Mark Rollins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12222899Abstract: A system and a method are disclosed for automatic content upload and process. The system retrieves a set of files from a source location based on instructions received from a client device of a user. The system then classifies the set of files into a plurality of categories corresponding to a sequence of one or more services configured to process or store files. The system then generates a data structure storing key values, where the key values are derived based on respective processing of subsets of files. Responsive to receiving an input to execute logic relating to the set of files, the system determines that the input is associated with one or more of the key values, retrieves the one or more of the key values, and executing the logic using the one or more retrieved key values.Type: GrantFiled: September 22, 2022Date of Patent: February 11, 2025Assignee: Docusign, Inc.Inventors: Timothy Seth, Mark Rollins
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Publication number: 20240104054Abstract: A system and a method are disclosed for automatic content upload and process. The system retrieves a set of files from a source location based on instructions received from a client device of a user. The system then classifies the set of files into a plurality of categories corresponding to a sequence of one or more services configured to process or store files. The system then generates a data structure storing key values, where the key values are derived based on respective processing of subsets of files. Responsive to receiving an input to execute logic relating to the set of files, the system determines that the input is associated with one or more of the key values, retrieves the one or more of the key values, and executing the logic using the one or more retrieved key values.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Timothy Seth, Mark Rollins
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Patent number: 10447211Abstract: A method and system for digital pre-distortion of an input signal to compensate for non-linear operation of a power amplifier. According to one aspect, some embodiments provide overlapping spline functions that are defined for two adjacent bins, where any two spline functions overlap in only one bin. Each spline function is computed as a function of one of an input signal envelope and a delayed signal envelope. According to another aspect, a tap weight evaluator includes a least mean squares, LMS, tap correlator updater configured to modulate a step size of an adaptation process to update each tap weight, the step size being modulated based on an approximate logarithm of the average power of the input to a tap weight computation.Type: GrantFiled: June 17, 2015Date of Patent: October 15, 2019Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mark Rollins, Arthur T. G. Fuller
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Publication number: 20180375480Abstract: A method and system for digital pre-distortion of an input signal to compensate for non-linear operation of a power amplifier. According to one aspect, some embodiments provide overlapping spline functions that are defined for two adjacent bins, where any two spline functions overlap in only one bin. Each spline function is computed as a function of one of an input signal envelope and a delayed signal envelope. According to another aspect, a tap weight evaluator includes a least mean squares, LMS, tap correlator updater configured to modulate a step size of an adaptation process to update each tap weight, the step size being modulated based on an approximate logarithm of the average power of the input to a tap weight computation.Type: ApplicationFiled: June 17, 2015Publication date: December 27, 2018Inventors: Mark ROLLINS, Arthur T.G. FULLER
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Patent number: 8983309Abstract: A transmitter in an optical communications system includes a digital signal processor for processing a data signal to generate a sample stream encoding successive symbols in accordance with a constrained phase modulation scheme having a constellation of at least two symbols and a modulation phase constrained to a phase range spanning less than 4?. A digital-to-analog converter converts the sample stream into a corresponding analog drive signal. A finite range phase modulator modulates a phase of a continuous wavelength channel light in accordance with the analog drive signal, to generate a modulated channel light for transmission through the optical communications system. A receiver in the optical communications system includes an optical stage for detecting phase and amplitude of the modulated channel light and for generating a corresponding sample stream, and a digital signal processor for processing the sample stream to estimate each successive symbol of the modulated channel light.Type: GrantFiled: February 13, 2012Date of Patent: March 17, 2015Assignee: Ciena CorporationInventors: James Harley, Douglas McGhan, Shahab Oveis Gharan, Kim B. Roberts, Mark Rollins
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Publication number: 20130209089Abstract: A transmitter in an optical communications system includes a digital signal processor for processing a data signal to generate a sample stream encoding successive symbols in accordance with a constrained phase modulation scheme having a constellation of at least two symbols and a modulation phase constrained to a phase range spanning less than 4?. A digital-to-analog converter converts the sample stream into a corresponding analog drive signal. A finite range phase modulator modulates a phase of a continuous wavelength channel light in accordance with the analog drive signal, to generate a modulated channel light for transmission through the optical communications system. A receiver in the optical communications system includes an optical stage for detecting phase and amplitude of the modulated channel light and for generating a corresponding sample stream, and a digital signal processor for processing the sample stream to estimate each successive symbol of the modulated channel light.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: CIENA CORPORATIONInventors: James HARLEY, Douglas MCGHAN, Shahab OVEIS GHARAN, Kim B. ROBERTS, Mark ROLLINS
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Patent number: 8300936Abstract: A system for improved display of tuned multi-scaled regions of an image with local and global control and methods for making and using same. To assist the novice user of image processing tool, less input parameters should be required. Further, it will assist the user if results are diplayed in a shorter period of time. Utilizing a hierarchical bottom-up approach provides for the advantage of being able to utilize intermediate results to gather more details. The systems and methods disclosed provide for the grouping of contiguous pixels which have similar properties. Further, the disclosed embodiments provide for the user the ability to see all levels of detail of segmentation either globally or locally. The scale-space is tuned to the information in the image.Type: GrantFiled: April 3, 2008Date of Patent: October 30, 2012Assignee: FlashFoto, Inc.Inventors: Robinson Piramuthu, Mark Rollins
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Publication number: 20090252429Abstract: Systems and methods for processing an initial digital image that comprises a foreground object and a background are provided in which the initial image is displayed on a display. A plurality of instances of an image segmentation technique are performed to the initial image, where the segmentation technique differentiates between the foreground object and the background in the initial image, thereby creating a plurality of processed images of the initial image. A first instance of the image segmentation technique uses a different parameter set than a second instance of the image segmentation technique. Each respective instance of the image segmentation technique creates a processed image corresponding to the respective instance of the image segmentation technique. Each such processed image is concurrently displayed at a time when the initial image is also displayed. A selection of a processed image in the plurality of processed images is then received for further processing.Type: ApplicationFiled: April 3, 2008Publication date: October 8, 2009Inventors: Dan Prochazka, Mark Rollins
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Publication number: 20080247648Abstract: A system for improved display of tuned multi-scaled regions of an image with local and global control and methods for making and using same. To assist the novice user of image processing tool, less input parameters should be required. Further, it will assist the user if results are diplayed in a shorter period of time. Utilizing a hierarchical bottom-up approach provides for the advantage of being able to utilize intermediate results to gather more details. The systems and methods disclosed provide for the grouping of contiguous pixels which have similar properties. Further, the disclosed embodiments provide for the user the ability to see all levels of detail of segmentation either globally or locally. The scale-space is tuned to the information in the image.Type: ApplicationFiled: April 3, 2008Publication date: October 9, 2008Inventors: Robinson Piramuthu, Mark Rollins
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Publication number: 20070033273Abstract: Programming and development infrastructure for an autonomic element is provided. The system includes a control plane (ISAC), a host server, a management console, and a module development environment. The ISAC contains an Autonomic Controller Engine (ACE) and management module(s). The management module is comprised of a set of scenarios. The ISAC is embedded in a control plane.Type: ApplicationFiled: April 17, 2006Publication date: February 8, 2007Inventors: Anthony White, Daniel Calvert, Fabio Katz, Mark Rollins, Jesse Stockall, David Sugden, Kenneth Webb, Jean-Marc Sequin, David Watson
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Patent number: 7080107Abstract: A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.Type: GrantFiled: July 6, 2004Date of Patent: July 18, 2006Assignee: Intel CorporationInventors: Daniel J. Pugh, Mark Rollins
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Publication number: 20050273480Abstract: A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.Type: ApplicationFiled: July 6, 2004Publication date: December 8, 2005Inventors: Daniel Pugh, Mark Rollins
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Patent number: 6834291Abstract: Embodiments for a gold code generator are generally described herein.Type: GrantFiled: October 27, 2000Date of Patent: December 21, 2004Assignee: Intel CorporationInventors: Daniel J. Pugh, Mark Rollins
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Publication number: 20030088757Abstract: A reconfigurable chip is described using a reconfigurable functional unit including a shifter unit, arithmetic logic unit and multiplexers. The data path units are interconnected to other data path units. The interconnection is preferably done by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. In a preferred embodiment the reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable functional unit instructions preferably are stored in a reconfigurable functional unit instruction memory which is addressed by a state machine on the chip.Type: ApplicationFiled: May 1, 2002Publication date: May 8, 2003Inventors: Joshua Lindner, Gary Lai, Bradley Taylor, Peter Lam, Mark Rollins, Vladimir Dinkevich, Craig B. Greenberg, Christopher E. Phillips, Hsin Wang
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Patent number: D532966Type: GrantFiled: May 17, 2005Date of Patent: December 5, 2006Inventor: Mark Rollins