Abstract: A programmable logic array (PLA) AND plane receives data input signals from input registers and generates corresponding minterms. The minterms are OR-ed together to form a sum of products, which are provided to output latches and clocked out before the end of each clock cycle by an internal self-timed signal as PLA output data. The OR plane (or the AND plane, or both) includes NOR gates that include a plurality of NMOS transistors. Each NMOS transistor in a gate has its drain connected to a common NOR gate output node, its source connected to ground and its gate connected to receive a corresponding minterm from the AND plane.

Abstract: The speed of large SRAMs is improved by embedding sense amplifiers into the SRAM core. In this way, the bit line length that the SRAM cells must drive is very short and, thus, the slew rate is fast. An additional layer of metal is employed to route and accumulate the sense amp results vertically over the entire SRAM core. To reduce the required pitch of the additional metal layers, a sense amp muxing scheme is also provided.

Abstract: A phase locked loop (PLL) circuit includes a phase comparator that compares the phases of an input signal and a feedback signal and generates UP and DOWN pulses that are related to the phase difference. A charge pump receives the UP and DOWN pulses from the phase comparator and either charges or discharges the tuning voltage of a loop filter. The voltage controlled oscillator (VCO) provides an output signal that has a frequency that is related to the tuning voltage. A frequency divider then divides the frequency of the VCO output by a factor of N and provides the output as the feedback signal to the phase comparator. The PLL includes pre-lock circuitry that responds to an active state of a pre-lock input signal by narrowing the dynamic range of the VCO to a pre-lock range that is centered around a predetermined final frequency and that deactivates upon achieving the pre-lock range.

Abstract: An integrated circuit memory structure includes a plurality of regular columns of memory cells arranged as a sequence such that each regular column except the last in the sequence has an associated adjacent regular column. Each regular column has associated sense amplifier circuitry and write driver circuitry for, respectively, reading output data from and writing input data to the regular column. At least one redundant column of memory cells is also provided. The structure also includes a programmable element that responds to a programming stimulus by providing a programming signal that identifies one of the regular columns as a defective column. Reconfiguration circuitry responds to the programming signal by reconfiguring the memory structure such that the sense amplifier circuitry and the write driver circuitry of each regular column in the sequence, beginning with the defective column, is reconfigured to be associated with the adjacent regular column.