Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Abstract: A Cartesian loop circuit includes a reference signal amplifier, a forward path coupled to the reference signal amplifier, a feedback path coupled to the forward path, and a controller. The forward path includes an up-mixer to up mix a forward path signal to a radio frequency signal. The feedback path includes a down-mixer to down mix a feedback signal to a frequency of a baseband reference signal inputted to the forward path. The feedback path provides the down-mixed feedback signal to the forward path. The controller is to perform power control at a low power by controlling a gain of the reference signal amplifier and is to perform power control at a high power by controlling a gain of the down-mixer. At the high power, the controller may perform power control by further controlling the gain of the up-mixer.

Abstract: A Cartesian loop circuit includes a reference signal amplifier, a forward path coupled to the reference signal amplifier, a feedback path coupled to the forward path, and a controller. The forward path includes an up-mixer to up mix a forward path signal to a radio frequency signal. The feedback path includes a down-mixer to down mix a feedback signal to a frequency of a baseband reference signal inputted to the forward path. The feedback path provides the down-mixed feedback signal to the forward path. The controller is to perform power control at a low power by controlling a gain of the reference signal amplifier and is to perform power control at a high power by controlling a gain of the down-mixer. At the high power, the controller may perform power control by further controlling the gain of the up-mixer.

Abstract: A Cartesian loop circuit includes a reference signal amplifier, a forward path coupled to the reference signal amplifier, a feedback path coupled to the forward path, and a controller. The forward path includes an up-mixer to up mix a forward path signal to a radio frequency signal. The feedback path includes a down-mixer to down mix a feedback signal to a frequency of a baseband reference signal inputted to the forward path. The feedback path provides the down-mixed feedback signal to the forward path. The controller is to perform power control at a low power by controlling a gain of the reference signal amplifier and is to perform power control at a high power by controlling a gain of the down-mixer. At the high power, the controller may perform power control by further controlling the gain of the up-mixer.

Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.

Abstract: A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

Abstract: A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode.

Abstract: A method and apparatus for a method and apparatus for correlation canceller for interference mitigation with adaptive DC offset cancellation for a dual mode communication device includes detecting an active signal transmitting in one mode; configuring integrators associated with the adaptive correlation canceller into gain amplifiers; detecting DC offset utilizing the gain amplifiers and comparators; and configuring the integrators from the gain amplifiers back to integrators with the DC offset applied thereto. The active signal transmitting in one mode can be Long Term Evolution (LTE) which is adjacent to a signal in another mode.

Abstract: A method and apparatus is provided for mitigating multiband self-interference using multipath cancellation. A dual-band transceiver receives an incoming radio-frequency signal that includes a multipath self-interference component generated by the transmission of an outgoing radio-frequency signal. The transceiver creates a plurality of reference signals from the outgoing radio-frequency signal by introducing delay values with respect to the outgoing signal. The transceiver adjusts the amplitude and phase of each of the delayed reference signals and combines the resulting signals with the incoming radio-frequency signal to cancel the self-interference component. The delay values may be determined adaptively. The systems and methods described herein are particularly useful for dual-band transceivers capable of communicating simultaneously using Long-Term Evolution (LTE) wideband signals and Public-Safety Narrowband (PSNB) signals.

Abstract: A method and apparatus is provided for mitigating multiband self-interference using multipath cancellation. A dual-band transceiver receives an incoming radio-frequency signal that includes a multipath self-interference component generated by the transmission of an outgoing radio-frequency signal. The transceiver creates a plurality of reference signals from the outgoing radio-frequency signal by introducing delay values with respect to the outgoing signal. The transceiver adjusts the amplitude and phase of each of the delayed reference signals and combines the resulting signals with the incoming radio-frequency signal to cancel the self-interference component. The delay values may be determined adaptively. The systems and methods described herein are particularly useful for dual-band transceivers capable of communicating simultaneously using Long-Term Evolution (LTE) wideband signals and Public-Safety Narrowband (PSNB) signals.

Abstract: A short, efficient antenna utilizing a floating coax transmission line over ground or overlapping wire feed structure for reduced antenna size for use in handheld radios. An asymmetric transmission line radiator having a length (LTL) is oriented substantially planar to and proximal to a truncated ground plane, and having at one end an input/output connector, and at an other end a feed point at least one of above a ground plane and proximal to its edge. An exciter antenna in a form of a plate or bent wire is coupled to the feed point and is exterior to the edge of the ground plane and oriented substantially orthogonal to the ground plane, the exciter antenna having a larger dimension length (LEA) that is at least 50% smaller than the length LTL. The overall length of a perimeter of the antenna is approximately ½ a wavelength of a center frequency of the antenna.

Abstract: Receivers (500) and methods of adaptively adjusting the receivers based on a received interferer are described. The peak-to-average ratio of a received signal is used to determine the type of interferer. The ratio and interferer type, in addition to the type of on-channel signal, are used to select parameters to adjust the decay time of a peak detector (516), and the threshold and hysteresis of a comparator (518). The peak detector (516) and comparator (518) are used to generate an off-channel flag that indicates the presence of a relatively strong interferer to other modules in the receiver (500). If valid data is not present a default set of parameters is provided. The ratio is determined by dividing the maximum peak over the average or a range of ratios is determined by comparing a scaled value of the average to different scaled values of the peak.

Abstract: A short, efficient antenna utilizing a floating coax transmission line over ground or overlapping wire feed structure for reduced antenna size for use in handheld radios. An asymmetric transmission line radiator having a length (LTL) is oriented substantially planar to and proximal to a truncated ground plane, and having at one end an input/output connector, and at an other end a feed point at least one of above a ground plane and proximal to its edge. An exciter antenna in a form of a plate or bent wire is coupled to the feed point and is exterior to the edge of the ground plane and oriented substantially orthogonal to the ground plane, the exciter antenna having a larger dimension length (LEA) that is at least 50% smaller than the length LTL. The overall length of a perimeter of the antenna is approximately ½ a wavelength of a center frequency of the antenna.

Abstract: Antenna apparatuses and methods used in wireless communication devices are disclosed. The antenna includes a first portion configured to be coupled to a communication device. The antenna also includes a second portion configured to be coupled to the first portion. The first portion and second portion are coupled by overlapping the first portion and second portion so as to produce an omnidirectional radiation pattern and a vertical radiation pattern.

Abstract: A linear RF transmitter (100) includes a forward path including a baseband signal combiner (109) and an RF (radio frequency) power amplifier (123), and a linearizing control loop from an output (127) of the RF power amplifier to an input of the combiner (109). A feedback control path (105, 107) of the loop delivers a baseband error control signal to the combiner. The transmitter further includes a test signal generator (102) to apply to the combiner in a closed loop level training mode a test signal comprising a voltage Vin which increases with time in a non-linear manner approaching an asymptotic limit such that in response an output signal produced by the combiner is a voltage Ve which is substantially constant over a period of time.

Abstract: A linear RF transmitter (100) includes a forward path including a baseband signal combiner (109) and an RF (radio frequency) power amplifier (123), and a linearizing control loop from an output (127) of the RF power amplifier to an input of the combiner (109). A feedback control path (105, 107) of the loop delivers a baseband error control signal to the combiner. The transmitter further includes a test signal generator (102) to apply to the combiner in a closed loop level training mode a test signal comprising a voltage Vin which increases with time in a non-linear manner approaching an asymptotic limit such that in response an output signal produced by the combiner is a voltage Ve which is substantially constant over a period of time.

Abstract: Receivers (500) and methods of adaptively adjusting the receivers based on a received interferer are described. The peak-to-average ratio of a received signal is used to determine the type of interferer. The ratio and interferer type, in addition to the type of on-channel signal, are used to select parameters to adjust the decay time of a peak detector (516), and the threshold and hysteresis of a comparator (518). The peak detector (516) and comparator (518) are used to generate an off-channel flag that indicates the presence of a relatively strong interferer to other modules in the receiver (500). If valid data is not present a default set of parameters is provided. The ratio is determined by dividing the maximum peak over the average or a range of ratios is determined by comparing a scaled value of the average to different scaled values of the peak.

Abstract: An integrated circuit includes a linearizer circuit in which excessive delay is compensated. The linearizer circuit includes a power amplifier, forward and feedback paths, and a microprocessor. A signal from the power amplifier is routed by the forward path to be transmitted while a portion of the signal to be transmitted is routed back to the power amplifier via the feedback path. The microprocessor applies phase training signals to the forward path. The microprocessor uses the phase training signals to determine the amount of delay in the linearizer circuit and alters the frequency position of poles and zeros in the linearizer circuit to compensate for the delay. The gain of the linearizer circuit is also altered by the microprocessor depending on the measured delay.

Abstract: Antenna apparatuses and methods used in wireless communication devices are disclosed. The antenna includes a first portion configured to be coupled to a communication device. The antenna also includes a second portion configured to be coupled to the first portion. The first portion and second portion are coupled by overlapping the first portion and second portion so as to produce an omnidirectional radiation pattern and a vertical radiation pattern.

Abstract: An antenna and methods for manufacturing the antenna is provided. The antenna (100) includes an electrically non-conductive substrate (102). The antenna further includes an electrically conductive strip (104). The electrically conductive strip (104) is wound around the electrically non-conductive substrate (102) so as to form an overlap (120) between adjacent turns of the electrically conductive strip (104), without creating a galvanic connection at the overlap.