Abstract: A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a pulse width modulation (PWM) signal from an inverter controller and adjust the received PWM signal based on a feedback signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to receive the adjusted PWM signal from the low voltage phase controller, provide the adjusted PWM signal to a phase switch, and provide the feedback signal based on an on-time measurement of the phase switch.

Abstract: A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a pulse width modulation (PWM) signal from an inverter controller and adjust the received PWM signal based on a feedback signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to receive the adjusted PWM signal from the low voltage phase controller, provide the adjusted PWM signal to a phase switch, and provide the feedback signal based on an on-time measurement of the phase switch.

Abstract: A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic interface configured to separate a high voltage area from a low voltage area; a low voltage message manager in the low voltage area; a high voltage message manager in the high voltage area, and configured to communicate with the low voltage message manager; and a point-of-use message manager in the high voltage area, and configured to communicate with the high voltage message manager.

Abstract: A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a pulse width modulation (PWM) signal from an inverter controller and adjust the received PWM signal based on a feedback signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to receive the adjusted PWM signal from the low voltage phase controller, provide the adjusted PWM signal to a phase switch, and provide the feedback signal based on an on-time measurement of the phase switch.

Abstract: A system comprises an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic isolator separating a high voltage area from a low voltage area; a low voltage phase controller in the low voltage area, the low voltage phase controller configured to receive a clock reference signal; and a high voltage phase controller in the high voltage area, the high voltage phase controller configured to align a clock reference signal of the high voltage phase controller with the clock reference signal of the low voltage phase controller.

Abstract: A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a galvanic interface configured to separate a high voltage area from a low voltage area; a low voltage message manager in the low voltage area; a high voltage message manager in the high voltage area, and configured to communicate with the low voltage message manager; and a point-of-use message manager in the high voltage area, and configured to communicate with the high voltage message manager.

Abstract: An analog signal gain circuit includes an input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force and an output providing an analog output signal defined by an amplified representation of the analog input signal and a dc offset component corresponding to a reference signal. A digital/analog feedback circuit includes a comparator having the reference signal as a switching threshold connected to an up/down counter having a number of digital outputs. The outputs of the up/down counter are connected to a D/A converter which converts the digital count to an analog feedback signal. The feedback signal is provided to the input of the analog signal gain circuit to minimize variations in the dc offset signal component of the analog output signal by compensating for the dc offset signal component of the analog input signal.

Abstract: A DC offset compensation circuit (34) for compensating for a DC offset voltage of a signal amplifier (24) includes a first sample and hold circuit (40) having an input receiving an amplifier output signal (VOUT2) and an output supplying the sampled and held output signal (VOUT2) to a non-inverting input of a comparator 42. A first digital-to-analog (D/A) circuit (46) is responsive to a number of digital input signals to produce an analog DC target signal at an output (VD) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (50) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator 42. The output of the comparator 42 is provided to an offset cancellation control circuit (56) including a state machine (66) and a counter circuit (68) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK1, CLK2, STRT, STP) and the comparator output signal (CO).

Abstract: A time-dependent piecewise linear signal generating circuit includes a first circuit responsive to a trigger signal to provide a number of time region signals each corresponding to a separate predefined time window of the piecewise linear signal, and a second circuit responsive to some of the time region signals to produce slope signals corresponding thereto, wherein each of the slope signals define a slope of the piecewise linear signal during a respective one of the time windows. A third circuit is responsive to the slope signals and the time region signals to produce the piecewise linear signal.

Abstract: A cross-coupled latch circuit that is a one-time programmable latch that allows volatile temporary writes to the latch prior to permanent programming of the latch. The latch circuit includes first and second programmable FET devices that include poly-poly capacitators in series with the gate terminal of each device. A pair of PMOS FET devices combine with the programmable devices to make up the latch. The latch circuit includes other FET devices that are switched on and off depending on whether the latch is being permanently programmed, temporarily written to, or reset. A NAND gate is provided such that a logical high output on the NAND gate allows the first programmable device to be temporarily programmed with a logical one and permanently programmed with a logical zero. A NOR gate is provided such that a logical high on the NOR gate allows the second programmable device to be temporarily programmed with a logical zero and permanently programmed with a logical one.