Patents by Inventor Mark S. Durschlag

Mark S. Durschlag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5646450
    Abstract: A semiconductor structure is described having a first electrode and a second electrode disposed on a surface of the structure and a bridging conductor connected between the first electrode and the second electrode. The bridging conductor includes a plurality of layers of different metals wherein the plurality of layers of different metals includes a layer of refractory metal adjacent a layer of electrically conductive metal. In a preferred embodiment, the refractory metal is titanium and the electrically conductive metal is gold. With such an arrangement, a semiconductor structure is provided which is effective in preventing restructuring due to mechanical stresses induced in the metal by dissimilar thermal expansion coefficients when electrical pulsing cycles the temperature of the semiconductor structure.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: July 8, 1997
    Assignee: Raytheon Company
    Inventors: Barry J. Liles, Mark S. Durschlag, James G. Oakes
  • Patent number: 4927784
    Abstract: A method of simultaneously forming recesses for via holes and tube structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single aperture such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ground plane conductor.
    Type: Grant
    Filed: September 28, 1988
    Date of Patent: May 22, 1990
    Assignee: Raytheon Company
    Inventors: Thomas E. Kazior, Mark S. Durschlag
  • Patent number: 4807022
    Abstract: A method of simultaneously forming recesses for via holes and tub structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single apertur such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ ground plane conductor.
    Type: Grant
    Filed: May 1, 1987
    Date of Patent: February 21, 1989
    Assignee: Raytheon Company
    Inventors: Thomas E. Kazior, Mark S. Durschlag
  • Patent number: 4670297
    Abstract: A first masking layer of a first resist is provided over a semiconductor substrate and is patterned in a selected region to provide a masked region over which an airbridge interconnect will be provided. A second relatively thick layer of a second, different type of resist and a third relatively thin layer of resist are provided, respectively, over the substrate. The second and third layers of resist are patterned to provide an aperture having overhanging portions exposing the previously applied patterned regions of the first layer, and selected adjacent portions of the substrate. The second and third layers may also be patterned to provide a region for a patterned strip conductor. A stream of evaporated metal is directed towards the substrate and deposited within the apertures to provide an airbridge interconnect conductor and patterned strip conductor.
    Type: Grant
    Filed: June 21, 1985
    Date of Patent: June 2, 1987
    Assignee: Raytheon Company
    Inventors: Kyu-Woong Lee, Mark S. Durschlag, John Day
  • Patent number: 4458295
    Abstract: Lumped passive components including a capacitor having a silicon nitride dielectric, a tantalum film resistor, and a capacitor having a tantalum oxide dielectric are formed on a semi-insulating substrate by first providing an insulating layer, here of silicon nitride, over the substrate and metal contacts having previously been formed on such substrate. The metal contacts provide a first plate for each one of such capacitors. A tantalum layer is reactively sputtered on the insulating layer, and a protective masking layer is next provided on such tantalum layer. An area where the anodized tantalum capacitor is to be formed is then opened in the protective masking layer over a selected one of the metal contacts. A portion of the tantalum is anodized in such area to form an area of a tantalum oxide (Ta.sub.2 O.sub.5). The area where the tantalum oxide is formed is confined generally to the area in the tantalum layer over the contact.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: July 3, 1984
    Assignee: Raytheon Company
    Inventors: Mark S. Durschlag, James L. Vorhaus