Abstract: A static random access memory having a static random access memory cell array, row address buffers for receiving row address signals, and column address buffers for receiving column address signals. The static random access memory also includes a clock chain circuit connected to the row address buffers and column address buffers such as to be responsive to transitions in the row address signals and column address signals by generating clock signals for accessing the static random access memory cell array. A method for accessing a static random access memory comprising detecting a transition occurring in a row address signal for addressing a static random access memory cell array; generating a plurality of clock signals in response to the transition in the row address signal; and accessing the static random access memory cell array.

Abstract: A circuit for connecting a memory cell matrix to voltage sources includes a voltage sensor responsive to the voltage levels of a first voltage source and of a second voltage source by producing a sense signal, and a voltage source coupler connected between the memory cell matrix and the voltage sensor. When the first voltage source voltage level is greater than a predetermined threshold voltage level, the sense signal causes the voltage source coupler to drive the first voltage source voltage level into the memory cell matrix. When the first voltage source voltage level falls to the threshold voltage level, the sense signal also causes the voltage source coupler to drive the second voltage source voltage level into the memory cell matrix to sustain memory cell data.

Abstract: The access time in reading data from a read only memory is enhanced by selectively inverting data stored in the memory. Each storage location along a wordline is weighted according to the distance of the bit location from the wordline driver, and bits stored therein are weighted by the bit location weight. The total weights of bits stored along the wordline are summed and compared with the maximum possible sum of weighted bits. If the ratio exceeds a preselected value, all bits of the wordline are inverted. The wordlines of a memory are provided with flag bits to indicate whether or not data stored on the wordline has been inverted.

Abstract: A high speed EPROM cell comprises two floating gate field effect transistors and one field effect transistor. One of the floating gate transistors is smaller than the other floating gate transistor and functions as a programming transistor in developing charge on the interconnected floating gates. The larger dimensions of the other floating gate transistor allows increased read current and operating speed. The field effect transistor connects the larger floating gate transistor to a read drain terminal. The cell is readily fabricated using two doped polycrystalline semiconductor lines and two metallization lines in accordance with conventional semiconductor processing techniques.

Abstract: A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative currents therein as an indication of threshold voltage parameters.

Abstract: An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain region and the floating gate. Dual paths are utilized to connect the tunnel region of the gate to the memory cell region of the gate.

Abstract: A programming pulse generating circuit, suitable for use on an electrically alterable read-only semiconductor memory, that decouples from the high voltage supply when in a standby condition so as to not draw current from the supply. Alternative voltage supply connections are effected by depletion mode devices.

Abstract: A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.

Abstract: A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to periodically drain away the control signal used to create the pulse.

Abstract: A metal-oxide-silicon (MOS), random-access memory (RAM) which is emitter-coupled logic (ECL) compatible and which does not require any high level clock inputs. The memory utilizes pseudo-static cells which are refreshed with an asynchronous charge-pump signal generated on the memory chip. Buffers utilize the ECL reference signal to assure ECL compatibility. The memory employs dynamic decoding in two separate levels of decoding.