Patents by Inventor Mark S FLETCHER

Mark S FLETCHER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10846219
    Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Thierry Fevrier, David F Heinrich, William C Hallowell, Mark S Fletcher, Justin Haanbyull Park, David W Engler
  • Publication number: 20200218599
    Abstract: Systems and methods provided for verifying the data integrity of a persistent memory device, may include: initiating a boot for a system including the persistent memory device; and determining whether a data integrity check setting is enabled for the boot. Furthermore, upon determining that a smart data integrity check condition is satisfied, a data integrity check for the persistent memory device can be executed. The data integrity check can include scanning data stored in the memory locations associated with the persistent memory device to detect whether at least one uncorrectable memory error is present within the persistent memory device. In the event at least one uncorrectable memory error is detected, writing each detected uncorrectable memory error to a memory error log, and communicated the memory error log to the Operating System (OS) of the system.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Inventors: ROBERT C. ELLIOTT, MARK S. FLETCHER, ROBERT VOLENTINE
  • Publication number: 20200073759
    Abstract: A scalable persistent memory for a computing resource includes a scalable persistent memory region allocated in system memory of the computing resource. In case of system shutdowns, the contents of the scalable persistent memory region is transferred to a backup storage resource. Transfers to the backup storage resource occur in data blocks consisting of a plurality of data lines. A data block may be rejected by the backup storage resource if the data block is found to contain data errors. For any data block rejected by the backup storage resource during a data transfer, the rejected block is scanned in data line increments and scrubbed by replacing or overwriting any data line found to contain an error with error-free data. A scrubbed block is then stored in a known good region of system memory previously determined to be error-free. The previously rejected data block is then transferred from the known good region to the backup storage resource.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Jason Spottswood, Marvin Spinhirne, Mark S. Fletcher
  • Publication number: 20190034252
    Abstract: A system includes a processor that includes a memory checker to access data from a memory and to set a processor corruption error (PCE) if a memory error is detected with the accessed data. The processor includes a status register to report the PCE and to identify a failed address from which the memory error was detected. An event handler receives the PCE and the failed address from the status register of the processor. The event handler blocks notification of the PCE to an operating system based on the failed address and notifies the operating system of the failed address to mitigate failure of the operating system.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Mark S Fletcher, Robert C Elliott
  • Publication number: 20180365147
    Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.
    Type: Application
    Filed: July 31, 2015
    Publication date: December 20, 2018
    Inventors: Thierry FEVRIER, David F HEINRICH, William C HALLOWELL, Mark S FLETCHER, Justin Haanbyull PARK, David W ENGLER