Patents by Inventor Mark S. Hefty
Mark S. Hefty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220210639Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 10, 2021Publication date: June 30, 2022Applicant: Intel CorporationInventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
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Patent number: 11246027Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.Type: GrantFiled: September 29, 2016Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
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Patent number: 10334047Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RMDA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: GrantFiled: September 26, 2017Date of Patent: June 25, 2019Assignee: Intel CorporationInventor: Mark S. Hefty
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Patent number: 10055371Abstract: Embodiments of apparatuses and methods for remote direct memory access (RDMA) with commit acknowledgements (ACKs) are described. In embodiments, a device may include a process queue to store a remote direct memory access (RDMA) request from an initiator to update a target memory. The device may further include a control module, coupled to the process queue, to issue a commit operation to the target memory based on the RDMA request and generate an acknowledgement, ACK, to be sent to the initiator on completion of the commit operation. Other embodiments may be described and/or claimed.Type: GrantFiled: November 3, 2014Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Mark S. Hefty, Robert J. Woodruff
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Publication number: 20180146038Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RMDA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: ApplicationFiled: September 26, 2017Publication date: May 24, 2018Applicant: Intel CorporationInventor: Mark S. Hefty
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Patent number: 9774677Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RDMA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: GrantFiled: April 10, 2012Date of Patent: September 26, 2017Assignee: Intel CorporationInventor: Mark S. Hefty
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Patent number: 9749413Abstract: Methods and apparatus to provide peer-to-peer interrupt signaling between devices coupled via one or more interconnects are described. In one embodiment, a NIC (Network Interface Card such as a Remote Direct Memory Access (RDMA) capable NIC) transfers data directly into or out of the memory of a peer device that is coupled to the NIC via one or more interconnects, bypassing a host computing/processing unit and/or main system memory. Other embodiments are also disclosed.Type: GrantFiled: May 29, 2012Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Mark S. Hefty, Robert J. Woodruff, Jerrie L. Coffman, William R. Magro
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Publication number: 20170104692Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.Type: ApplicationFiled: September 29, 2016Publication date: April 13, 2017Inventors: WILLIAM R. MAGRO, TODD M. RIMMER, ROBERT J. WOODRUFF, MARK S. HEFTY, SAYANTAN SUR
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Patent number: 9560117Abstract: An embodiment includes a low-latency mechanism for performing a checkpoint on a distributed application. More specifically, an embodiment of the invention includes processing a first application on a compute node, which is included in a cluster, to produce first computed data and then storing the first computed data in volatile memory included locally in the compute node; halting the processing of the first application, based on an initiated checkpoint, and storing first state data corresponding to the halted first application in the volatile memory; storing the first state information and the first computed data in non-volatile memory included locally in the compute node; and resuming processing of the halted first application and then continuing the processing the first application to produce second computed data while simultaneously pulling the first state information and the first computed data from the non-volatile memory to an input/output (IO) node.Type: GrantFiled: December 30, 2011Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Mark S. Hefty, Arlin Davis, Robert Woodruff, Sayantan Sur, Shiow-wen Cheng
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Patent number: 9495324Abstract: One embodiment provides a method for receiving subnet administration (SA) data using a remote direct memory access (RDMA) transfer. The method includes formatting, by a network node element, an SA data query with an RDMA-capable flag; configuring, by the network node element, a reliably-connected queue pair (RCQP) to receive an RDMA transfer from a subnet manager in communication with the network node element on an RDMA-capable network; and allocating, by the network node element, an RDMA write target buffer to receive the SA data using an RDMA transfer from the subnet manager in response to the SA data query.Type: GrantFiled: March 26, 2013Date of Patent: November 15, 2016Assignee: Intel CorporationInventor: Mark S. Hefty
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Patent number: 9490988Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RMDA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: GrantFiled: April 10, 2012Date of Patent: November 8, 2016Assignee: Intel CorporationInventor: Mark S. Hefty
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Patent number: 9479506Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.Type: GrantFiled: April 16, 2014Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
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Publication number: 20160124877Abstract: Embodiments of apparatuses and methods for remote direct memory access (RDMA) with commit acknowledgements (ACKs) are described. In embodiments, a device may include a process queue to store a remote direct memory access (RDMA) request from an initiator to update a target memory. The device may further include a control module, coupled to the process queue, to issue a commit operation to the target memory based on the RDMA request and generate an acknowledgement, ACK, to be sent to the initiator on completion of the commit operation. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 3, 2014Publication date: May 5, 2016Inventors: Mark S. Hefty, Robert J. Woodruff
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Patent number: 9288160Abstract: Methods, systems, and apparatus for extending the size of Infiniband subnets using GID switching in an Infiniband fabric. An Infiniband subnet is defined to include multiple local identifier (LID) domains, each including multiple nodes interconnected via one or more LID switches. In turn, the LID domains are interconnected via one or more GID switches. Messages may be transferred between nodes in a given LID domain using LID switches in the domain. Messages may be transferred between nodes in separate LID domains by routing the messages via one or more GID switches. In various embodiments, GID switches may be implemented to also operate as LID switches and perform routing based on selected packet header fields.Type: GrantFiled: August 23, 2011Date of Patent: March 15, 2016Assignee: Intel CorporationInventor: Mark S. Hefty
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Publication number: 20150305006Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.Type: ApplicationFiled: April 16, 2014Publication date: October 22, 2015Inventors: WILLIAM R. MAGRO, TODD M. RIMMER, ROBERT J. WOODRUFF, MARK S. HEFTY, SAYANTAN SUR
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Publication number: 20140250202Abstract: Methods and apparatus to provide peer-to-peer interrupt signaling between devices coupled via one or more interconnects are described. In one embodiment, a NIC (Network Interface Card such as a Remote Direct Memory Access (RDMA) capable NIC) transfers data directly into or out of the memory of a peer device that is coupled to the NIC via one or more interconnects, bypassing a host computing/processing unit and/or main system memory. Other embodiments are also disclosed.Type: ApplicationFiled: May 29, 2012Publication date: September 4, 2014Inventors: Mark S. Hefty, Robert J. Woodruff, Jerrie L. Coffman, William R. Margo
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Publication number: 20140207896Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RMDA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: ApplicationFiled: April 10, 2012Publication date: July 24, 2014Inventor: Mark S. Hefty
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Publication number: 20140201306Abstract: The present disclosure provides systems and methods for remote direct memory access (RDMA) with reduced latency. RDMA allows information to be transferred directly between memory buffers in networked devices without the need for substantial processing. While RDMA requires registration/deregistration for buffers that are not already preregistered, RDMA with reduced latency transfers information to intermediate buffers during registration/deregistration, utilizing time that would have ordinarily been wasted waiting for these processes to complete, and reducing the amount of information to transfer while the source buffer is registered. In this way the RDMA transaction may be completed more quickly. RDMA with reduced latency may be employed to expedite various information transactions. For example, RMDA with reduced latency may be utilized to stream information within a device, or may be used to transfer information for an information source external to the device directly to an application buffer.Type: ApplicationFiled: April 10, 2012Publication date: July 17, 2014Inventor: Mark S. Hefty
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Publication number: 20140129635Abstract: An embodiment includes a low-latency mechanism for performing a checkpoint on a distributed application. More specifically, an embodiment of the invention includes processing a first application on a compute node, which is included in a cluster, to produce first computed data and then storing the first computed data in volatile memory included locally in the compute node; halting the processing of the first application, based on an initiated checkpoint, and storing first state data corresponding to the halted first application in the volatile memory; storing the first state information and the first computed data in non-volatile memory included locally in the compute node; and resuming processing of the halted first application and then continuing the processing the first application to produce second computed data while simultaneously pulling the first state information and the first computed data from the non-volatile memory to an input/output (IO) node.Type: ApplicationFiled: December 30, 2011Publication date: May 8, 2014Inventors: Mark S. Hefty, Arlin Davis, Robert Woodruff, Sayantan Sur, Shiow-wen Cheng
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Publication number: 20130259033Abstract: Methods, systems, and apparatus for extending the size of Infiniband subnets using GID switching in an Infiniband fabric. An Infiniband subnet is defined to include multiple local identifier (LID) domains, each including multiple nodes interconnected via one or more LID switches. In turn, the LID domains are interconnected via one or more GID switches. Messages may be transferred between nodes in a given LID domain using LID switches in the domain. Messages may be transferred between nodes in separate LID domains by routing the messages via one or more GID switches. In various embodiments, GID switches may be implemented to also operate as LID switches and perform routing based on selected packet header fields.Type: ApplicationFiled: August 23, 2011Publication date: October 3, 2013Inventor: Mark S. Hefty